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Fixed WE/RE usage in iCE40 BRAM mapping

This commit is contained in:
Clifford Wolf 2015-11-24 10:51:34 +01:00
parent c86fbae3d1
commit 8ff229a3ea
1 changed files with 8 additions and 8 deletions
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16
techlibs/ice40/brams_map.v
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@ -213,14 +213,14 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1E
.RDATA(A1DATA), .RDATA(A1DATA),
.RADDR(A1ADDR_11), .RADDR(A1ADDR_11),
.RCLK(CLK2), .RCLK(CLK2),
.RCLKE(1'b1), .RCLKE(A1EN),
.RE(A1EN), .RE(1'b1),
.WDATA(B1DATA), .WDATA(B1DATA),
.WADDR(B1ADDR_11), .WADDR(B1ADDR_11),
.MASK(~B1EN), .MASK(~B1EN),
.WCLK(CLK3), .WCLK(CLK3),
.WCLKE(1'b1), .WCLKE(|B1EN),
.WE(|B1EN) .WE(1'b1)
); );
endmodule endmodule
@ -299,13 +299,13 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B
.RDATA(A1DATA_16), .RDATA(A1DATA_16),
.RADDR(A1ADDR_11), .RADDR(A1ADDR_11),
.RCLK(CLK2), .RCLK(CLK2),
.RCLKE(1'b1), .RCLKE(A1EN),
.RE(A1EN), .RE(1'b1),
.WDATA(B1DATA_16), .WDATA(B1DATA_16),
.WADDR(B1ADDR_11), .WADDR(B1ADDR_11),
.WCLK(CLK3), .WCLK(CLK3),
.WCLKE(1'b1), .WCLKE(|B1EN),
.WE(|B1EN) .WE(1'b1)
); );
endmodule endmodule