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As per @daveshah1 remove async DFF timing from xilinx

This commit is contained in:
Eddie Hung 2019-06-14 12:43:20 -07:00
parent 7876b5b8be
commit 8fa74287a7
1 changed files with 2 additions and 2 deletions
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4
techlibs/xilinx/abc_xc7.box
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@ -54,9 +54,9 @@ FDSE 7 0 4 1
# Inputs: C CE CLR D # Inputs: C CE CLR D
# Outputs: Q # Outputs: Q
FDCE 8 0 4 1 FDCE 8 0 4 1
- - 404 - - - - -
# Inputs: C CE D PRE # Inputs: C CE D PRE
# Outputs: Q # Outputs: Q
FDPE 9 0 4 1 FDPE 9 0 4 1
- - - 404 - - - -