mirror of https://github.com/YosysHQ/yosys.git
Fix multiclock for btor2 witness
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parent
29c0a59589
commit
8fa2f3b260
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@ -1313,8 +1313,10 @@ struct SimWorker : SimShared
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void run_cosim_btor2_witness(Module *topmod)
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void run_cosim_btor2_witness(Module *topmod)
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{
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{
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log_assert(top == nullptr);
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log_assert(top == nullptr);
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if ((clock.size()+clockn.size())==0)
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if (!multiclock && (clock.size()+clockn.size())==0)
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log_error("Clock signal must be specified.\n");
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log_error("Clock signal must be specified.\n");
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if (multiclock && (clock.size()+clockn.size())>0)
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log_error("For multiclock witness there should be no clock signal.\n");
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std::ifstream f;
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std::ifstream f;
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f.open(sim_filename.c_str());
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f.open(sim_filename.c_str());
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if (f.fail() || GetSize(sim_filename) == 0)
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if (f.fail() || GetSize(sim_filename) == 0)
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@ -1347,10 +1349,12 @@ struct SimWorker : SimShared
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set_inports(clockn, State::S0);
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set_inports(clockn, State::S0);
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update();
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update();
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register_output_step(10*cycle+0);
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register_output_step(10*cycle+0);
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if (!multiclock) {
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set_inports(clock, State::S0);
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set_inports(clock, State::S0);
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set_inports(clockn, State::S1);
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set_inports(clockn, State::S1);
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update();
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update();
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register_output_step(10*cycle+5);
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register_output_step(10*cycle+5);
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}
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cycle++;
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cycle++;
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prev_cycle = curr_cycle;
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prev_cycle = curr_cycle;
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}
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}
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