riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix O(N^2) port dump down to O(N)

This commit is contained in:
Akash Levy 2024-11-16 22:56:41 -08:00
parent 81011ad926
commit 8f9a0b680a
1 changed files with 17 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
backends/verilog/verilog_backend.cc
View File

@ -2334,10 +2334,17 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
bool keep_running = true;
int cnt = 0;
for (int port_id = 1; keep_running; port_id++) {
keep_running = false;
int max_port_id = 0;
for (auto wire : module->wires()) {
if (wire->port_id == port_id) {
max_port_id = std::max(wire->port_id, max_port_id);
}
std::vector<Wire *> wires(max_port_id + 1, nullptr);
for (auto wire : module->wires()) {
wires[wire->port_id] = wire;
}
for (int port_id = 1; port_id <= max_port_id; port_id++) {
Wire *wire = wires[port_id];
if (wire) {
if (port_id != 1)
f << stringf(", ");
f << stringf("%s", id(wire->name).c_str());
@ -2346,7 +2353,6 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
continue;
}
}
}
f << stringf(");\n");
if (!systemverilog && !module->processes.empty()) {
initial_id = NEW_ID;