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Added DDFR support

This commit is contained in:
Miodrag Milanovic 2024-07-24 13:00:56 +02:00
parent 1a6e5c671f
commit 8f806c0d12
2 changed files with 138 additions and 21 deletions
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54
techlibs/nanoxplore/cells_sim_u.v
View File

@ -250,3 +250,57 @@ module NX_WFG_U(R, SI, ZI, SO, ZO);
$error("Unknown NX_WFG_U mode"); $error("Unknown NX_WFG_U mode");
endgenerate endgenerate
endmodule endmodule
module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);
input CK;
input CKF;
input R;
input I;
input I2;
input L;
output O;
output O2;
parameter location = "";
parameter path = 0;
parameter dff_type = 1'b0;
parameter dff_sync = 1'b0;
parameter dff_load = 1'b0;
wire load = dff_load ? 1'b1 : L; // reversed when compared to DFF
wire async_reset = !dff_sync && R;
wire sync_reset = dff_sync && R;
generate
if (path==1) begin
// IDDFR
always @(posedge CK, posedge async_reset)
if (async_reset) O <= dff_type;
else if (sync_reset) O <= dff_type;
else if (load) O <= I;
always @(posedge CKF, posedge async_reset)
if (async_reset) O2 <= dff_type;
else if (sync_reset) O2 <= dff_type;
else if (load) O2 <= I;
end
else if (path==0 || path==2) begin
reg q1, q2;
// ODDFR
always @(posedge CK, posedge async_reset)
if (async_reset) q1 <= dff_type;
else if (sync_reset) q1 <= dff_type;
else if (load) q1 <= I;
always @(posedge CKF, posedge async_reset)
if (async_reset) q2 <= dff_type;
else if (sync_reset) q2 <= dff_type;
else if (load) q2 <= I2;
assign O = CK ? q1 : q2;
end
else
$error("Unknown NX_DDFR_U path");
endgenerate
endmodule

105
techlibs/nanoxplore/cells_wrap_u.v
View File

@ -1,18 +1,82 @@
module NX_ODDFR_U(CK,R,I1,I2,L,O);
input CK;
input R;
input I1;
input I2;
input L;
output O;
parameter location = "";
parameter path = 0;
parameter dff_type = 1'b0;
parameter dff_sync = 1'b0;
parameter dff_load = 1'b0;
NX_DDFR_U #(
.location(location),
.path(path),
.dff_type(dff_type),
.dff_sync(dff_sync),
.dff_load(dff_load)
) _TECHMAP_REPLACE_ (
.CK(CK),
.CKF(CK),
.R(R),
.I(I1),
.I2(I2),
.L(L),
.O(O),
.O2()
);
endmodule
module NX_IDDFR_U(CK,R,I,L,O1,O2);
input CK;
input R;
input I;
input L;
output O1;
output O2;
parameter location = "";
parameter dff_type = 1'b0;
parameter dff_sync = 1'b0;
parameter dff_load = 1'b0;
NX_DDFR_U #(
.location(location),
.path(1),
.dff_type(dff_type),
.dff_sync(dff_sync),
.dff_load(dff_load)
) _TECHMAP_REPLACE_ (
.CK(CK),
.CKF(CK),
.R(R),
.I(I),
.I2(1'b0),
.L(L),
.O(O1),
.O2(O2)
);
endmodule
module NX_CKS_U(CKI, CMD, CKO); module NX_CKS_U(CKI, CMD, CKO);
input CKI; input CKI;
output CKO; output CKO;
input CMD; input CMD;
NX_GCK_U #( NX_GCK_U #(
.inv_in(1'b0), .inv_in(1'b0),
.inv_out(1'b0), .inv_out(1'b0),
.std_mode("CKS") .std_mode("CKS")
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.CMD(CMD), .CMD(CMD),
.SI1(CKI), .SI1(CKI),
.SI2(), .SI2(),
.SO(CKO) .SO(CKO)
); );
endmodule endmodule
module NX_CMUX_U(CKI0, CKI1, SEL, CKO); module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
@ -21,16 +85,16 @@ module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
output CKO; output CKO;
input SEL; input SEL;
NX_GCK_U #( NX_GCK_U #(
.inv_in(1'b0), .inv_in(1'b0),
.inv_out(1'b0), .inv_out(1'b0),
.std_mode("MUX") .std_mode("MUX")
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.CMD(SEL), .CMD(SEL),
.SI1(CKI0), .SI1(CKI0),
.SI2(CKI1), .SI2(CKI1),
.SO(CKO) .SO(CKO)
); );
endmodule endmodule
module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI); module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI);
@ -3440,4 +3504,3 @@ module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hs
parameter rx_usrclk_use_pcs_clk_2 = 1'b0; parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
parameter tx_usrclk_use_pcs_clk_2 = 1'b0; parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
endmodule endmodule