From 8f42d6dacea3ea3fab5862ecb6ac77f33b28a90e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 13 Mar 2024 09:48:16 +0100
Subject: [PATCH] fifo

---
 techlibs/nanoxplore/cells_bb.v     | 198 ---------------
 techlibs/nanoxplore/cells_bb_u.v   | 127 ++++++++++
 techlibs/nanoxplore/cells_wrap_u.v | 386 +++++++++++++++++++++++++++++
 3 files changed, 513 insertions(+), 198 deletions(-)

diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index a9d18edee..e5207ad34 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -165,158 +165,6 @@ module NX_ECC(CKD, CHK, COR, ERR);
     output ERR;
 endmodule
 
-(* blackbox *)
-module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);
-    input [17:0] I;
-    output [17:0] O;
-    input [5:0] RAI;
-    output [5:0] RAO;
-    input RCK;
-    output REQ;
-    input RRSTI;
-    output RRSTO;
-    input [5:0] WAI;
-    output [5:0] WAO;
-    input WCK;
-    input WE;
-    input WEA;
-    output WEQ;
-    input WRSTI;
-    output WRSTO;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 6'b000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
-, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
-, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23
-, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7
-, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2
-, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);
-    input I1;
-    input I10;
-    input I11;
-    input I12;
-    input I13;
-    input I14;
-    input I15;
-    input I16;
-    input I17;
-    input I18;
-    input I19;
-    input I2;
-    input I20;
-    input I21;
-    input I22;
-    input I23;
-    input I24;
-    input I25;
-    input I26;
-    input I27;
-    input I28;
-    input I29;
-    input I3;
-    input I30;
-    input I31;
-    input I32;
-    input I33;
-    input I34;
-    input I35;
-    input I36;
-    input I4;
-    input I5;
-    input I6;
-    input I7;
-    input I8;
-    input I9;
-    output O1;
-    output O10;
-    output O11;
-    output O12;
-    output O13;
-    output O14;
-    output O15;
-    output O16;
-    output O17;
-    output O18;
-    output O19;
-    output O2;
-    output O20;
-    output O21;
-    output O22;
-    output O23;
-    output O24;
-    output O25;
-    output O26;
-    output O27;
-    output O28;
-    output O29;
-    output O3;
-    output O30;
-    output O31;
-    output O32;
-    output O33;
-    output O34;
-    output O35;
-    output O36;
-    output O4;
-    output O5;
-    output O6;
-    output O7;
-    output O8;
-    output O9;
-    input RAI1;
-    input RAI2;
-    input RAI3;
-    input RAI4;
-    input RAI5;
-    input RAI6;
-    input RAI7;
-    output RAO1;
-    output RAO2;
-    output RAO3;
-    output RAO4;
-    output RAO5;
-    output RAO6;
-    output RAO7;
-    input RCK;
-    output REQ1;
-    output REQ2;
-    input RRSTI;
-    output RRSTO;
-    input WAI1;
-    input WAI2;
-    input WAI3;
-    input WAI4;
-    input WAI5;
-    input WAI6;
-    input WAI7;
-    output WAO1;
-    output WAO2;
-    output WAO3;
-    output WAO4;
-    output WAO5;
-    output WAO6;
-    output WAO7;
-    input WCK;
-    input WE;
-    input WEA;
-    output WEQ1;
-    output WEQ2;
-    input WRSTI;
-    output WRSTO;
-    parameter mode = 0;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 7'b0000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
 (* blackbox *)
 module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
 , usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
@@ -3395,52 +3243,6 @@ module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD
     parameter weakTermination = "";
 endmodule
 
-(* blackbox *)
-module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
-    input [35:0] I;
-    output [35:0] O;
-    input [5:0] RAI;
-    output [5:0] RAO;
-    input RCK;
-    output REQ;
-    input RRSTI;
-    input [5:0] WAI;
-    output [5:0] WAO;
-    input WCK;
-    input WE;
-    input WEA;
-    output WEQ;
-    input WRSTI;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 7'b0000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
-(* blackbox *)
-module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);
-    input [17:0] I;
-    output [17:0] O;
-    input [6:0] RAI;
-    output [6:0] RAO;
-    input RCK;
-    output [1:0] REQ;
-    input RRSTI;
-    input [6:0] WAI;
-    output [6:0] WAO;
-    input WCK;
-    input WE;
-    input WEA;
-    output [1:0] WEQ;
-    input WRSTI;
-    parameter rck_edge = 1'b0;
-    parameter read_addr_inv = 7'b0000000;
-    parameter use_read_arst = 1'b0;
-    parameter use_write_arst = 1'b0;
-    parameter wck_edge = 1'b0;
-endmodule
-
 (* blackbox *)
 module SMACC24x18_1DSP(clk, rst, A, B, Z);
     input [23:0] A;
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
index f828ebb3a..598eb8d2c 100644
--- a/techlibs/nanoxplore/cells_bb_u.v
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -2451,3 +2451,130 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
     parameter wck_edge = 1'b0;
 endmodule
 
+
+(* blackbox *)
+module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
+, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
+, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23
+, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7
+, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2
+, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);
+    input I1;
+    input I10;
+    input I11;
+    input I12;
+    input I13;
+    input I14;
+    input I15;
+    input I16;
+    input I17;
+    input I18;
+    input I19;
+    input I2;
+    input I20;
+    input I21;
+    input I22;
+    input I23;
+    input I24;
+    input I25;
+    input I26;
+    input I27;
+    input I28;
+    input I29;
+    input I3;
+    input I30;
+    input I31;
+    input I32;
+    input I33;
+    input I34;
+    input I35;
+    input I36;
+    input I4;
+    input I5;
+    input I6;
+    input I7;
+    input I8;
+    input I9;
+    output O1;
+    output O10;
+    output O11;
+    output O12;
+    output O13;
+    output O14;
+    output O15;
+    output O16;
+    output O17;
+    output O18;
+    output O19;
+    output O2;
+    output O20;
+    output O21;
+    output O22;
+    output O23;
+    output O24;
+    output O25;
+    output O26;
+    output O27;
+    output O28;
+    output O29;
+    output O3;
+    output O30;
+    output O31;
+    output O32;
+    output O33;
+    output O34;
+    output O35;
+    output O36;
+    output O4;
+    output O5;
+    output O6;
+    output O7;
+    output O8;
+    output O9;
+    input RAI1;
+    input RAI2;
+    input RAI3;
+    input RAI4;
+    input RAI5;
+    input RAI6;
+    input RAI7;
+    output RAO1;
+    output RAO2;
+    output RAO3;
+    output RAO4;
+    output RAO5;
+    output RAO6;
+    output RAO7;
+    input RCK;
+    output REQ1;
+    output REQ2;
+    input RRSTI;
+    output RRSTO;
+    input WAI1;
+    input WAI2;
+    input WAI3;
+    input WAI4;
+    input WAI5;
+    input WAI6;
+    input WAI7;
+    output WAO1;
+    output WAO2;
+    output WAO3;
+    output WAO4;
+    output WAO5;
+    output WAO6;
+    output WAO7;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ1;
+    output WEQ2;
+    input WRSTI;
+    output WRSTO;
+    parameter mode = 0;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
index eda3565b3..3c9eba1aa 100644
--- a/techlibs/nanoxplore/cells_wrap_u.v
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -2133,3 +2133,389 @@ module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13,
   assign COR=1'b0;
   assign ERR=1'b0;
 endmodule
+
+module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);
+    input [17:0] I;
+    output [17:0] O;
+    input [5:0] RAI;
+    output [5:0] RAO;
+    input RCK;
+    output REQ;
+    input RRSTI;
+    output RRSTO;
+    input [5:0] WAI;
+    output [5:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ;
+    input WRSTI;
+    output WRSTO;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 6'b000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_FIFO_U #(
+    .mode(0),
+    .wck_edge(wck_edge),
+    .rck_edge(rck_edge),
+    .read_addr_inv(read_addr_inv),
+    .use_write_arst(use_write_arst),
+    .use_read_arst(use_read_arst)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .WE(WE),
+    .WEA(WEA),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .WRSTI(WRSTI),
+    .WAI1(WAI[0]),
+    .WAI2(WAI[1]),
+    .WAI3(WAI[2]),
+    .WAI4(WAI[3]),
+    .WAI5(WAI[4]),
+    .WAI6(WAI[5]),
+    .WAI7(1'b0),
+    .WRSTO(WRSTO),
+    .WAO1(WAO[0]),
+    .WAO2(WAO[1]),
+    .WAO3(WAO[2]),
+    .WAO4(WAO[3]),
+    .WAO5(WAO[4]),
+    .WAO6(WAO[5]),
+    .WEQ1(WEQ),
+    .RRSTI(RRSTI),
+    .RAI1(RAI[0]),
+    .RAI2(RAI[1]),
+    .RAI3(RAI[2]),
+    .RAI4(RAI[3]),
+    .RAI5(RAI[4]),
+    .RAI6(RAI[5]),
+    .RAI7(1'b0),
+    .RRSTO(RRSTO),
+    .RAO1(RAO[0]),
+    .RAO2(RAO[1]),
+    .RAO3(RAO[2]),
+    .RAO4(RAO[3]),
+    .RAO5(RAO[4]),
+    .RAO6(RAO[5]),
+    .REQ1(REQ)
+  );
+endmodule
+
+module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);
+    input [17:0] I;
+    output [17:0] O;
+    input [6:0] RAI;
+    output [6:0] RAO;
+    input RCK;
+    output [1:0] REQ;
+    input RRSTI;
+    input [6:0] WAI;
+    output [6:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output [1:0] WEQ;
+    input WRSTI;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_FIFO_U #(
+    .mode(1),
+    .wck_edge(wck_edge),
+    .rck_edge(rck_edge),
+    .read_addr_inv(read_addr_inv),
+    .use_write_arst(use_write_arst),
+    .use_read_arst(use_read_arst)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .WE(WE),
+    .WEA(WEA),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(1'b0),
+    .I20(1'b0),
+    .I21(1'b0),
+    .I22(1'b0),
+    .I23(1'b0),
+    .I24(1'b0),
+    .I25(1'b0),
+    .I26(1'b0),
+    .I27(1'b0),
+    .I28(1'b0),
+    .I29(1'b0),
+    .I30(1'b0),
+    .I31(1'b0),
+    .I32(1'b0),
+    .I33(1'b0),
+    .I34(1'b0),
+    .I35(1'b0),
+    .I36(1'b0),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .WRSTI(WRSTI),
+    .WAI1(WAI[0]),
+    .WAI2(WAI[1]),
+    .WAI3(WAI[2]),
+    .WAI4(WAI[3]),
+    .WAI5(WAI[4]),
+    .WAI6(WAI[5]),
+    .WAI7(WAI[6]),
+    .WAO1(WAO[0]),
+    .WAO2(WAO[1]),
+    .WAO3(WAO[2]),
+    .WAO4(WAO[3]),
+    .WAO5(WAO[4]),
+    .WAO6(WAO[5]),
+    .WAO7(WAO[6]),
+    .WEQ1(WEQ[0]),
+    .WEQ2(WEQ[1]),
+    .RRSTI(RRSTI),
+    .RAI1(RAI[0]),
+    .RAI2(RAI[1]),
+    .RAI3(RAI[2]),
+    .RAI4(RAI[3]),
+    .RAI5(RAI[4]),
+    .RAI6(RAI[5]),
+    .RAI7(RAI[6]),
+    .RAO1(RAO[0]),
+    .RAO2(RAO[1]),
+    .RAO3(RAO[2]),
+    .RAO4(RAO[3]),
+    .RAO5(RAO[4]),
+    .RAO6(RAO[5]),
+    .RAO7(RAO[6]),
+    .REQ1(REQ[0]),
+    .REQ2(REQ[1])
+  );
+endmodule
+
+module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
+    input [35:0] I;
+    output [35:0] O;
+    input [5:0] RAI;
+    output [5:0] RAO;
+    input RCK;
+    output REQ;
+    input RRSTI;
+    input [5:0] WAI;
+    output [5:0] WAO;
+    input WCK;
+    input WE;
+    input WEA;
+    output WEQ;
+    input WRSTI;
+    parameter rck_edge = 1'b0;
+    parameter read_addr_inv = 7'b0000000;
+    parameter use_read_arst = 1'b0;
+    parameter use_write_arst = 1'b0;
+    parameter wck_edge = 1'b0;
+
+  NX_FIFO_U #(
+    .mode(2),
+    .wck_edge(wck_edge),
+    .rck_edge(rck_edge),
+    .read_addr_inv(read_addr_inv),
+    .use_write_arst(use_write_arst),
+    .use_read_arst(use_read_arst)
+  ) _TECHMAP_REPLACE_ (
+    .RCK(RCK),
+    .WCK(WCK),
+    .WE(WE),
+    .WEA(WEA),
+    .I1(I[0]),
+    .I2(I[1]),
+    .I3(I[2]),
+    .I4(I[3]),
+    .I5(I[4]),
+    .I6(I[5]),
+    .I7(I[6]),
+    .I8(I[7]),
+    .I9(I[8]),
+    .I10(I[9]),
+    .I11(I[10]),
+    .I12(I[11]),
+    .I13(I[12]),
+    .I14(I[13]),
+    .I15(I[14]),
+    .I16(I[15]),
+    .I17(I[16]),
+    .I18(I[17]),
+    .I19(I[18]),
+    .I20(I[19]),
+    .I21(I[20]),
+    .I22(I[21]),
+    .I23(I[22]),
+    .I24(I[23]),
+    .I25(I[24]),
+    .I26(I[25]),
+    .I27(I[26]),
+    .I28(I[27]),
+    .I29(I[28]),
+    .I30(I[29]),
+    .I31(I[30]),
+    .I32(I[31]),
+    .I33(I[32]),
+    .I34(I[33]),
+    .I35(I[34]),
+    .I36(I[35]),
+    .O1(O[0]),
+    .O2(O[1]),
+    .O3(O[2]),
+    .O4(O[3]),
+    .O5(O[4]),
+    .O6(O[5]),
+    .O7(O[6]),
+    .O8(O[7]),
+    .O9(O[8]),
+    .O10(O[9]),
+    .O11(O[10]),
+    .O12(O[11]),
+    .O13(O[12]),
+    .O14(O[13]),
+    .O15(O[14]),
+    .O16(O[15]),
+    .O17(O[16]),
+    .O18(O[17]),
+    .O19(O[18]),
+    .O20(O[19]),
+    .O21(O[20]),
+    .O22(O[21]),
+    .O23(O[22]),
+    .O24(O[23]),
+    .O25(O[24]),
+    .O26(O[25]),
+    .O27(O[26]),
+    .O28(O[27]),
+    .O29(O[28]),
+    .O30(O[29]),
+    .O31(O[30]),
+    .O32(O[31]),
+    .O33(O[32]),
+    .O34(O[33]),
+    .O35(O[34]),
+    .O36(O[35]),
+    .WRSTI(WRSTI),
+    .WAI1(WAI[0]),
+    .WAI2(WAI[1]),
+    .WAI3(WAI[2]),
+    .WAI4(WAI[3]),
+    .WAI5(WAI[4]),
+    .WAI6(WAI[5]),
+    .WAI7(1'b0),
+    .WAO1(WAO[0]),
+    .WAO2(WAO[1]),
+    .WAO3(WAO[2]),
+    .WAO4(WAO[3]),
+    .WAO5(WAO[4]),
+    .WAO6(WAO[5]),
+    .WEQ1(WEQ),
+    .RRSTI(RRSTI),
+    .RAI1(RAI[0]),
+    .RAI2(RAI[1]),
+    .RAI3(RAI[2]),
+    .RAI4(RAI[3]),
+    .RAI5(RAI[4]),
+    .RAI6(RAI[5]),
+    .RAI7(1'b0),
+    .RAO1(RAO[0]),
+    .RAO2(RAO[1]),
+    .RAO3(RAO[2]),
+    .RAO4(RAO[3]),
+    .RAO5(RAO[4]),
+    .RAO6(RAO[5]),
+    .REQ1(REQ)
+  );
+endmodule
\ No newline at end of file