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Revert "write_xaiger to not use module POs but only write outputs if driven" 

This reverts commit 0ab1e496dc.
This commit is contained in:
Eddie Hung 2019-11-22 13:24:28 -08:00
parent c761fa49b7
commit 8ef241c6f4
1 changed files with 10 additions and 22 deletions
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32
backends/aiger/xaiger.cc
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@ -542,30 +542,18 @@ struct XAigerWriter
} }
for (auto bit : unused_bits) for (auto bit : unused_bits)
if (holes_mode) undriven_bits.erase(bit);
undriven_bits.erase(bit);
else if (!undriven_bits.count(bit))
output_bits.insert(bit);
if (!holes_mode) { if (!undriven_bits.empty() && !holes_mode) {
for (auto port : module->ports) { bool whole_module = module->design->selected_whole_module(module->name);
auto wire = module->wire(port); undriven_bits.sort();
if (!wire->port_output) for (auto bit : undriven_bits) {
continue; if (whole_module)
for (int i = 0; i < GetSize(wire); i++) { log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
SigBit wirebit(wire, i); input_bits.insert(bit);
SigBit bit = sigmap(wirebit);
if (bit == State::Sx)
continue;
if (!undriven_bits.count(bit)) {
output_bits.insert(wirebit);
}
}
} }
if (whole_module)
if (!undriven_bits.empty()) log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
for (auto bit : undriven_bits)
input_bits.insert(bit);
} }
if (holes_mode) { if (holes_mode) {