mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactor
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commit
8eb5bb258c
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@ -219,14 +219,14 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe
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for (size_t pos = abc9_script.find("{R}"); pos != std::string::npos; pos = abc9_script.find("{R}", pos))
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abc9_script = abc9_script.substr(0, pos) + R + abc9_script.substr(pos+3);
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abc9_script += stringf("; &ps -l; &write -n %s/output.aig;", tempdir_name.c_str());
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abc9_script += stringf("; &ps -l; &write -n %s/output.aig", tempdir_name.c_str());
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if (design->scratchpad_get_bool("abc9.verify")) {
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if (dff_mode)
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abc9_script += "verify -s;";
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abc9_script += "; verify -s";
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else
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abc9_script += "verify;";
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abc9_script += "; verify";
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}
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abc9_script += "time";
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abc9_script += "; time";
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abc9_script = add_echos_to_abc9_cmd(abc9_script);
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for (size_t i = 0; i+1 < abc9_script.size(); i++)
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@ -95,6 +95,8 @@ void prep_dff(RTLIL::Module *module)
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SigSpec abc9_init = assign_map(abc9_init_wire);
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if (!abc9_init.is_fully_const())
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log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
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if (abc9_init == State::S1)
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log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module));
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r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
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log_assert(r2.second);
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}
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