riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Changed NEW_WIRE API to return the wire, not the signal

This commit is contained in:
Clifford Wolf 2013-10-18 14:19:45 +02:00
parent bfa1a65fa9
commit 8e8f1994b8
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
kernel/rtlil.cc
View File

@ -382,7 +382,7 @@ RTLIL::Module *RTLIL::Module::clone() const
return new_mod; return new_mod;
} }
RTLIL::SigSpec RTLIL::Module::new_wire(int width, RTLIL::IdString name) RTLIL::Wire *RTLIL::Module::new_wire(int width, RTLIL::IdString name)
{ {
RTLIL::Wire *wire = new RTLIL::Wire; RTLIL::Wire *wire = new RTLIL::Wire;
wire->width = width; wire->width = width;

2
kernel/rtlil.h
View File

@ -247,7 +247,7 @@ struct RTLIL::Module {
virtual size_t count_id(RTLIL::IdString id); virtual size_t count_id(RTLIL::IdString id);
virtual void check(); virtual void check();
virtual void optimize(); virtual void optimize();
RTLIL::SigSpec new_wire(int width, RTLIL::IdString name); RTLIL::Wire *new_wire(int width, RTLIL::IdString name);
void add(RTLIL::Wire *wire); void add(RTLIL::Wire *wire);
void add(RTLIL::Cell *cell); void add(RTLIL::Cell *cell);
void fixup_ports(); void fixup_ports();