mirror of https://github.com/YosysHQ/yosys.git
Cleanup
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@ -17,10 +17,9 @@ input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam cmp_width = `LUT_WIDTH/2;
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generate
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if (_TECHMAP_CELLTYPE_ == "" || (A_WIDTH <= cmp_width || B_WIDTH <= cmp_width))
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if (_TECHMAP_CELLTYPE_ == "")
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wire _TECHMAP_FAIL_ = 1;
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else if (_TECHMAP_CELLTYPE_ == "$lt") begin
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// Transform $lt into $gt by swapping A and B
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@ -30,45 +29,43 @@ generate
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// Transform $le into $ge by swapping A and B
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$ge #(.A_SIGNED(B_SIGNED), .B_SIGNED(A_SIGNED), .A_WIDTH(B_WIDTH), .B_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(B), .B(A), .Y(Y));
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end
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else begin
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else if (A_WIDTH != B_WIDTH) begin
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// Perform sign extension on A and B
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localparam WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
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wire [WIDTH-1:0] AA = {{(WIDTH-A_WIDTH){A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
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wire [WIDTH-1:0] BB = {{(WIDTH-B_WIDTH){B_SIGNED ? B[B_WIDTH-1] : 1'b0}}, B};
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// Compute width of $lcu/carry-chain cell
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localparam lcu_width = (WIDTH+cmp_width-1)/cmp_width;
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if (_TECHMAP_CELLTYPE_ == "$gt")
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$gt #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(WIDTH), .B_WIDTH(WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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else if (_TECHMAP_CELLTYPE_ == "$ge")
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$ge #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(WIDTH), .B_WIDTH(WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));
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else
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wire _TECHMAP_FAIL_ = 1;
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end
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else begin
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localparam cmp_width = `LUT_WIDTH/2;
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localparam lcu_width = (A_WIDTH+cmp_width-1)/cmp_width;
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wire [lcu_width-1:0] P, G, CO;
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genvar i, j;
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integer j;
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for (i = 0; i < WIDTH; i=i+cmp_width) begin
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for (i = 0; i < A_WIDTH; i=i+cmp_width) begin
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wire [cmp_width-1:0] PP, GG;
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if (i < WIDTH-cmp_width) begin
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for (j = cmp_width-1; j >= 0 && i+j < A_WIDTH; j = j-1) begin
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// Bit-wise equality (xnor) of sign-extended A and B
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assign PP = AA[i +: cmp_width] ^~ BB[i +: cmp_width];
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// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
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// from MSB down, deferring to less significant bits if the
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// MSBs are equal
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assign GG[cmp_width-1] = AA[i+cmp_width-1] & ~BB[i+cmp_width-1];
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for (j = cmp_width-2; j >= 0; j=j-1)
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assign GG[j] = &PP[cmp_width-1:j+1] & (AA[i+j] & ~BB[i+j]);
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// Propagate only if all bits are equal
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// (inconclusive evidence to say A >= B)
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assign P[i/cmp_width] = &PP;
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// Generate if any pairs call for it
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assign G[i/cmp_width] = |GG;
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end
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else begin
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assign PP = AA[WIDTH-1:i] ^~ BB[WIDTH-1:i];
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if (A_SIGNED && B_SIGNED)
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assign GG[WIDTH-i-1] = ~AA[WIDTH-1] & BB[WIDTH-1];
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assign PP[j] = A[i+j] ^~ B[i+j];
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if (i+j == A_WIDTH-1 && A_SIGNED && B_SIGNED)
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assign GG[j] = ~A[i+j] & B[i+j];
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else if (j == cmp_width-1)
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assign GG[j] = A[i+j] & ~B[i+j];
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else
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assign GG[WIDTH-i-1] = AA[WIDTH-1] & ~BB[WIDTH-1];
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for (j = WIDTH-i-2; j >= 0; j=j-1)
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assign GG[j] = &PP[WIDTH-i-1:j+1] & (AA[i+j] & ~BB[i+j]);
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assign P[i/cmp_width] = &PP[WIDTH-i-1:0];
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assign G[i/cmp_width] = |GG[WIDTH-i-1:0];
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// Priority "encoder" that checks A[i] == 1'b1 && B[i] == 1'b0
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// from MSB down, deferring to less significant bits if the
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// MSBs are equal
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assign GG[j] = &PP[cmp_width-1:j+1] & (A[i+j] & ~B[i+j]);
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end
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// Propagate only if all bit pairs are equal
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// (inconclusive evidence to say A >= B)
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assign P[i/cmp_width] = &PP;
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// Generate if any bit pairs call for it
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assign G[i/cmp_width] = |GG;
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end
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// For $ge operation, start with the assumption that A and B are
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// equal (propagating this equality if A and B turn out to be so)
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