add assertions for synth_microchip tests

techlibs/microchip/arith_map.v

@@ -31,9 +31,9 @@ endmodule
 
 (* techmap_celltype = "$reduce_xor" *)
 module \$__microchip_XOR8_ (A, Y);
-	parameter A_SIGNED = 0;
-	parameter A_WIDTH = 0;
-	parameter Y_WIDTH = 0;
+	parameter A_SIGNED = 1;
+	parameter A_WIDTH = 8;
+	parameter Y_WIDTH = 1;
 
 	input [A_WIDTH-1:0] A;
 	output [Y_WIDTH-1:0] Y;

tests/arch/microchip/.gitignore

@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
+*.vm
+

tests/arch/microchip/Registers.v

@@ -21,7 +21,7 @@ module Registers(
 	input en,
 	input rst,
 	input D,
-	output Q
+	output reg Q
 );
 parameter LOAD_DATA = 1;
 

tests/arch/microchip/Registers.ys

@@ -19,5 +19,6 @@ read_verilog Registers.v
 
 synth_microchip -top Registers -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr Registers.vm
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CLKBUF %% t:* %D

tests/arch/microchip/carryout.ys

@@ -18,4 +18,5 @@ read_verilog carryout.v
 
 synth_microchip -top carryout -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr carryout.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/cascade.ys

@@ -18,4 +18,5 @@ read_verilog cascade.v
 
 synth_microchip -top cascade -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr cascade.vm
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/dff_opt.ys

@@ -13,9 +13,12 @@
 # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
 read_verilog dff_opt.v 
 
 synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr dff_opt.vm
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CFG4
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D

tests/arch/microchip/full_dsp.ys

@@ -18,4 +18,5 @@ read_verilog full_dsp.v
 
 synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr full_dsp.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/large_mult.ys

@@ -18,4 +18,6 @@ read_verilog large_mult.v
 
 synth_microchip -top large_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr large_mult.vm
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+

tests/arch/microchip/mac.ys

@@ -20,5 +20,5 @@ read_verilog mac.v
 # run the synth flow, specifies top module and additional parameters
 synth_microchip -top mac -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr mac.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/postAdd_mult.ys

@@ -18,4 +18,5 @@ read_verilog postAdd_mult.v
 
 synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr postAdd_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/post_adder.ys

@@ -16,6 +16,8 @@
 
 read_verilog post_adder.v
 
-synth_microchip -top post_adder -abc9 -family polarfire
+synth_microchip -top post_adder -abc9 -family polarfire -noiopad
+
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
 
-write_verilog -noexpr post_adder.vm

tests/arch/microchip/pre_adder_dsp.ys

@@ -18,4 +18,5 @@ read_verilog pre_adder_dsp.v
 
 synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr pre_adder_dsp.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/ram_SDP.ys

@@ -18,4 +18,7 @@ read_verilog ram_SDP.v
 
 synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr ram_SDP.vm
+select -assert-count 1 t:RAM1K20
+select -assert-count 1 t:CFG1
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
+

tests/arch/microchip/ram_TDP.ys

@@ -18,4 +18,5 @@ read_verilog ram_TDP.v
 
 synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
 
-write_verilog -noexpr ram_TDP.vm
+select -assert-count 1 t:RAM1K20
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/reduce.ys

@@ -18,4 +18,6 @@ read_verilog reduce.v
 
 synth_microchip -top reduce -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reduce.vm
+select -assert-count 1 t:XOR8
+select -assert-none t:XOR8 %% t:* %D
+

tests/arch/microchip/reg_c.ys

@@ -18,4 +18,5 @@ read_verilog reg_c.v
 
 synth_microchip -top reg_c -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reg_c.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/reg_test.ys

@@ -18,4 +18,5 @@ read_verilog reg_test.v
 
 synth_microchip -top reg_test -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reg_test.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/run-test.sh

@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"

tests/arch/microchip/signed_mult.ys

@@ -18,4 +18,5 @@ read_verilog signed_mult.v
 
 synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr signed_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/simple_ram.ys

@@ -18,4 +18,5 @@ read_verilog simple_ram.v
 
 synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr simple_ram.vm
+select -assert-count 1 t:RAM1K20
+select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/unsigned_mult.ys

@@ -18,4 +18,5 @@ read_verilog unsigned_mult.v
 
 synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr unsigned_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D

tests/arch/microchip/uram_ar.v

@@ -17,9 +17,9 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module uram_ar(data,waddr,we,clk,q);
-parameter d_width = 27;
+parameter d_width = 12;
 parameter addr_width = 2;
-parameter mem_depth = 4;
+parameter mem_depth = 12;
 input [d_width-1:0] data;
 input [addr_width-1:0] waddr;
 input we, clk;

tests/arch/microchip/uram_ar.ys

@@ -18,4 +18,5 @@ read_verilog uram_ar.v
 
 synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr uram_ar.vm
+select -assert-count 1 t:RAM64x12
+select -assert-none t:RAM64x12 %% t:* %D

tests/arch/microchip/uram_sr.ys

@@ -18,4 +18,5 @@ read_verilog uram_sr.v
 
 synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr uram_sr.vm
+select -assert-count 1 t:RAM64x12
+select -assert-none t:RAM64x12 %% t:* %D

tests/arch/microchip/widemux.v

@@ -23,25 +23,8 @@ module widemux(
 	output Y
 
 );
+assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
 
-wire A, B;
-
-always @ (*) begin 
-		if (S0)begin
-		A = data[1];
-		B = data[3];
-		end else begin 
-		A = data[0];
-		B = data[2];
-	end
-
-	if (S1)begin
-		Y = A;
-	end else begin
-		Y = B;
-	end
-
-end
 endmodule
 
 

tests/arch/microchip/widemux.ys

@@ -18,4 +18,5 @@ read_verilog widemux.v
 
 synth_microchip -top widemux -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr widemux.vm
+select -assert-count 1 t:MX4
+select -assert-none t:MX4 %% t:* %D