From 8e508f2a2ade89e5e301de18c922155698ae6960 Mon Sep 17 00:00:00 2001
From: mszelwiga <mszelwiga@internships.antmicro.com>
Date: Fri, 8 Nov 2024 15:41:20 +0100
Subject: [PATCH] Fix setting bits of parameters in setundef pass

This commit also adds test that verifies correctness of this change.
---
 passes/cmds/setundef.cc   |  2 +-
 tests/various/setundef.sv | 10 ++++++++++
 tests/various/setundef.ys |  8 ++++++++
 3 files changed, 19 insertions(+), 1 deletion(-)
 create mode 100644 tests/various/setundef.sv
 create mode 100644 tests/various/setundef.ys

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 4ba58036b..dce33c05b 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -243,7 +243,7 @@ struct SetundefPass : public Pass {
 			{
 				for (auto *cell : module->selected_cells()) {
 					for (auto &parameter : cell->parameters) {
-						for (auto bit : parameter.second) {
+						for (auto &bit : parameter.second.bits()) {
 							if (bit > RTLIL::State::S1)
 								bit = worker.next_bit();
 						}
diff --git a/tests/various/setundef.sv b/tests/various/setundef.sv
new file mode 100644
index 000000000..59a553fbb
--- /dev/null
+++ b/tests/various/setundef.sv
@@ -0,0 +1,10 @@
+module foo #(parameter [1:0] a) (output [1:0] o);
+	assign o = a;
+endmodule
+
+module top(output [1:0] o);
+	foo #(2'b0x) foo(o);
+	always_comb begin
+		assert(o == 2'b00);
+	end
+endmodule
diff --git a/tests/various/setundef.ys b/tests/various/setundef.ys
new file mode 100644
index 000000000..269e5a40f
--- /dev/null
+++ b/tests/various/setundef.ys
@@ -0,0 +1,8 @@
+read_verilog -sv setundef.sv
+setundef -zero -params
+hierarchy -top top
+flatten
+proc
+async2sync
+write_json
+sat -seq 5 -prove-asserts