mirror of https://github.com/YosysHQ/yosys.git
Add "write_edif -attrprop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -106,6 +106,9 @@ struct EdifBackend : public Backend {
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log(" if the design contains constant nets. use \"hilomap\" to map to custom\n");
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log(" constant drivers first)\n");
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log("\n");
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log(" -attrprop\n");
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log(" create EDIF properties for cell attributes\n");
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log("\n");
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log(" -pvector {par|bra|ang}\n");
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log(" sets the delimiting character for module port rename clauses to\n");
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log(" parentheses, square brackets, or angle brackets.\n");
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@ -121,6 +124,7 @@ struct EdifBackend : public Backend {
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log_header(design, "Executing EDIF backend.\n");
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std::string top_module_name;
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bool port_rename = false;
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bool attr_properties = false;
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std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
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bool nogndvcc = false;
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CellTypes ct(design);
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@ -137,6 +141,10 @@ struct EdifBackend : public Backend {
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nogndvcc = true;
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continue;
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}
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if (args[argidx] == "-attrprop") {
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attr_properties = true;
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continue;
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}
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if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
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std::string parray;
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port_rename = true;
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@ -332,24 +340,33 @@ struct EdifBackend : public Backend {
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*f << stringf(" (instance %s\n", EDIF_DEF(cell->name));
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*f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
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lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
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for (auto &p : cell->parameters)
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if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
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*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
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else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
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*f << stringf("\n (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
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auto add_prop = [&](IdString name, Const val) {
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if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
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*f << stringf("\n (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
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else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
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*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
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else {
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std::string hex_string = "";
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for (size_t i = 0; i < p.second.bits.size(); i += 4) {
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for (size_t i = 0; i < val.bits.size(); i += 4) {
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int digit_value = 0;
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if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
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if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
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if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
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if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
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if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
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if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
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if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
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if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
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char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
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hex_string = std::string(digit_str) + hex_string;
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}
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*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
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*f << stringf("\n (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
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}
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};
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for (auto &p : cell->parameters)
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add_prop(p.first, p.second);
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if (attr_properties)
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for (auto &p : cell->attributes)
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add_prop(p.first, p.second);
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*f << stringf(")\n");
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for (auto &p : cell->connections()) {
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RTLIL::SigSpec sig = sigmap(p.second);
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