mirror of https://github.com/YosysHQ/yosys.git
Bugfix in opt_const $eq -> buffer code
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@ -524,11 +524,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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RTLIL::SigSpec a = assign_map(cell->getPort("\\A"));
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RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
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if (a.is_fully_const()) {
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if (a.is_fully_const() && !b.is_fully_const()) {
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cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type.str());
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RTLIL::SigSpec tmp = cell->getPort("\\A");
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cell->setPort("\\A", cell->getPort("\\B"));
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cell->setPort("\\B", tmp);
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cell->setPort("\\A", b);
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cell->setPort("\\B", a);
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std::swap(a, b);
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}
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if (b.is_fully_const()) {
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