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Fix mul2dsp signedness

This commit is contained in:
Eddie Hung 2019-07-17 12:44:52 -07:00
parent 1b62b82e05
commit 8dca8d486e
1 changed files with 38 additions and 42 deletions
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18
techlibs/common/mul2dsp.v
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@ -34,25 +34,21 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y;
generate
localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED;
localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED;
if (add_sign_A || add_sign_B) begin
if (add_sign_A && add_sign_B)
if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin
wire [1:0] dummy;
else
wire dummy;
\$mul #(
.A_SIGNED(1),
.B_SIGNED(1),
.A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)),
.B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)),
.Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0))
.A_WIDTH(A_WIDTH + 1),
.B_WIDTH(B_WIDTH + 1),
.Y_WIDTH(Y_WIDTH + 2)
) _TECHMAP_REPLACE_ (
.A(add_sign_A ? {1'b0, A} : A),
.B(add_sign_B ? {1'b0, B} : B),
.A({1'b0, A}),
.B({1'b0, B}),
.Y({dummy, Y})
);
end
// NB: A_SIGNED == B_SIGNED == 0 from here
else if (A_WIDTH >= B_WIDTH)
\$__mul_gen #(
.A_SIGNED(A_SIGNED),