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Fix mul2dsp signedness

This commit is contained in:
Eddie Hung 2019-07-17 12:44:52 -07:00
parent 1b62b82e05
commit 8dca8d486e
1 changed files with 38 additions and 42 deletions
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80
techlibs/common/mul2dsp.v
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@ -34,49 +34,45 @@ module \$mul (A, B, Y);
output [Y_WIDTH-1:0] Y; output [Y_WIDTH-1:0] Y;
generate generate
localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED; if (`DSP_A_SIGNEDONLY && `DSP_B_SIGNEDONLY && !A_SIGNED) begin
localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED; wire [1:0] dummy;
if (add_sign_A || add_sign_B) begin \$mul #(
if (add_sign_A && add_sign_B) .A_SIGNED(1),
wire [1:0] dummy; .B_SIGNED(1),
else .A_WIDTH(A_WIDTH + 1),
wire dummy; .B_WIDTH(B_WIDTH + 1),
\$mul #( .Y_WIDTH(Y_WIDTH + 2)
.A_SIGNED(1), ) _TECHMAP_REPLACE_ (
.B_SIGNED(1), .A({1'b0, A}),
.A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)), .B({1'b0, B}),
.B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)), .Y({dummy, Y})
.Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0)) );
) _TECHMAP_REPLACE_ (
.A(add_sign_A ? {1'b0, A} : A),
.B(add_sign_B ? {1'b0, B} : B),
.Y({dummy, Y})
);
end end
else if (A_WIDTH >= B_WIDTH) // NB: A_SIGNED == B_SIGNED == 0 from here
\$__mul_gen #( else if (A_WIDTH >= B_WIDTH)
.A_SIGNED(A_SIGNED), \$__mul_gen #(
.B_SIGNED(B_SIGNED), .A_SIGNED(A_SIGNED),
.A_WIDTH(A_WIDTH), .B_SIGNED(B_SIGNED),
.B_WIDTH(B_WIDTH), .A_WIDTH(A_WIDTH),
.Y_WIDTH(Y_WIDTH) .B_WIDTH(B_WIDTH),
) _TECHMAP_REPLACE_ ( .Y_WIDTH(Y_WIDTH)
.A(A), ) _TECHMAP_REPLACE_ (
.B(B), .A(A),
.Y(Y) .B(B),
); .Y(Y)
else );
\$__mul_gen #( else
.A_SIGNED(B_SIGNED), \$__mul_gen #(
.B_SIGNED(A_SIGNED), .A_SIGNED(B_SIGNED),
.A_WIDTH(B_WIDTH), .B_SIGNED(A_SIGNED),
.B_WIDTH(A_WIDTH), .A_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH) .B_WIDTH(A_WIDTH),
) _TECHMAP_REPLACE_ ( .Y_WIDTH(Y_WIDTH)
.A(B), ) _TECHMAP_REPLACE_ (
.B(A), .A(B),
.Y(Y) .B(A),
); .Y(Y)
);
endgenerate endgenerate
endmodule endmodule