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abc9: suppress warnings when no compatible + used flop boxes formed

This commit is contained in:
Eddie Hung 2020-04-15 15:41:55 -07:00
parent cdd250ef16
commit 8d7b3c06b2
3 changed files with 66 additions and 38 deletions
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61
passes/techmap/abc9.cc
View File

@ -281,41 +281,52 @@ struct Abc9Pass : public ScriptPass
if (check_label("dff", "(only if -dff)")) { if (check_label("dff", "(only if -dff)")) {
if (dff_mode || help_mode) { if (dff_mode || help_mode) {
run("abc9_ops -prep_dff_hier"); // derive all used (* abc9_flop *) modules, run("abc9_ops -prep_dff_hier"); // derive all used (* abc9_flop *) modules,
// create stubs in $abc9_unmap design // create stubs in $abc9_unmap design
run("design -stash $abc9"); run("design -stash $abc9");
run("design -copy-from $abc9 @$abc9_flops"); // copy derived modules in run("design -copy-from $abc9 @$abc9_flops"); // copy derived modules in
run("proc"); run("proc");
run("wbflip"); run("wbflip");
run("techmap"); run("techmap");
run("opt"); run("opt");
if (!help_mode)
active_design->scratchpad_unset("abc9_ops.prep_dff_map.did_something");
run("abc9_ops -prep_dff_map"); // rewrite specify run("abc9_ops -prep_dff_map"); // rewrite specify
// select all $_DFF_[NP]_ bool did_something = help_mode || active_design->scratchpad_get_bool("abc9_ops.prep_dff_map.did_something");
// then select all its fanins if (did_something) {
// then select all fanouts of all that // select all $_DFF_[NP]_
// lastly remove $_DFF_[NP]_ cells // then select all its fanins
run("setattr -set submod \"$abc9_flop\" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d"); // then select all fanouts of all that
run("submod"); // lastly remove $_DFF_[NP]_ cells
run("design -copy-to $abc9 *_$abc9_flop"); // copy submod out run("setattr -set submod \"$abc9_flop\" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d");
run("delete *_$abc9_flop"); run("submod");
if (help_mode) { run("design -copy-to $abc9 *_$abc9_flop"); // copy submod out
run("foreach module in design"); run("delete *_$abc9_flop");
run(" rename <module-name>_$abc9_flop _TECHMAP_REPLACE_"); if (help_mode) {
run("foreach module in design");
run(" rename <module-name>_$abc9_flop _TECHMAP_REPLACE_");
}
else {
// Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs
for (auto module : active_design->selected_modules()) {
active_design->selected_active_module = module->name.str();
if (module->cell(stringf("%s_$abc9_flop", module->name.c_str())))
run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
}
}
run("design -stash $abc9_map");
run("design -load $abc9");
run("design -delete $abc9");
run("select -unset $abc9_flops");
run("techmap -wb -map %$abc9_map"); // techmap user design into submod + $_DFF_[NP]_
run("design -delete $abc9_map");
run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
run("abc9_ops -prep_dff_unmap"); // implement $abc9_unmap design
} }
else { else {
// Rename all submod-s to _TECHMAP_REPLACE_ to inherit name + attrs run("design -load $abc9");
for (auto module : active_design->selected_modules()) { run("design -delete $abc9");
active_design->selected_active_module = module->name.str(); run("select -unset $abc9_flops");
run(stringf("rename %s_$abc9_flop _TECHMAP_REPLACE_", module->name.c_str()));
}
} }
run("design -stash $abc9_map");
run("design -load $abc9");
run("design -delete $abc9");
run("select -unset $abc9_flops");
run("abc9_ops -prep_dff_unmap"); // implement $abc9_unmap design
run("techmap -map %$abc9_map"); // techmap user design into submod + $_DFF_[NP]_
run("design -delete $abc9_map");
run("setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop");
} }
} }

39
passes/techmap/abc9_ops.cc
View File

@ -161,10 +161,23 @@ void prep_dff_hier(RTLIL::Design *design)
void prep_dff_map(RTLIL::Design *design) void prep_dff_map(RTLIL::Design *design)
{ {
Design *unmap_design = saved_designs.at("$abc9_unmap");
for (auto module : design->modules()) { for (auto module : design->modules()) {
vector<Cell*> specify_cells; vector<Cell*> specify_cells;
SigBit D, Q; SigBit D, Q;
Cell* dff_cell = nullptr; Cell* dff_cell = nullptr;
// If module has a public name (i.e. not $paramod) and it doesn't exist
// in the $abc9_unmap then it means only derived modules were
// instantiated, so make this a blackbox
if (module->name[0] == '\\' && !unmap_design->module(module->name.str() + "_$abc9_flop")) {
module->makeblackbox();
module->set_bool_attribute(ID::blackbox, false);
module->set_bool_attribute(ID::whitebox, true);
continue;
}
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
if (dff_cell) if (dff_cell)
@ -185,6 +198,7 @@ void prep_dff_map(RTLIL::Design *design)
log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(module), log_id(cell->type)); log_warning("Module '%s' contains a %s cell with non-zero initial state -- this is not unsupported for ABC9 sequential synthesis. Treating as a blackbox.\n", log_id(module), log_id(cell->type));
module->makeblackbox(); module->makeblackbox();
module->set_bool_attribute(ID::blackbox, false);
auto wire = module->addWire(ID(_TECHMAP_FAIL_)); auto wire = module->addWire(ID(_TECHMAP_FAIL_));
wire->set_bool_attribute(ID::keep); wire->set_bool_attribute(ID::keep);
@ -215,19 +229,20 @@ void prep_dff_map(RTLIL::Design *design)
D = w; D = w;
} }
if (GetSize(specify_cells) == 0) { if (GetSize(specify_cells) == 0)
log_warning("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module)); log_error("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
}
else { // Rewrite $specify cells that end with $_DFF_[NP]_.Q
// Rewrite $specify cells that end with $_DFF_[NP]_.Q // to $_DFF_[NP]_.D since it will be moved into
// to $_DFF_[NP]_.D since it will be moved into // the submodule
// the submodule for (auto cell : specify_cells) {
for (auto cell : specify_cells) { auto DST = cell->getPort(ID::DST);
auto DST = cell->getPort(ID::DST); DST.replace(Q, D);
DST.replace(Q, D); cell->setPort(ID::DST, DST);
cell->setPort(ID::DST, DST);
}
} }
design->scratchpad_set_bool("abc9_ops.prep_dff_map.did_something", true);
continue_outer_loop: ; continue_outer_loop: ;
} }
} }

4
tests/arch/xilinx/abc9_dff.ys
View File

@ -14,6 +14,7 @@ endmodule
EOT EOT
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt design -load postopt
select -assert-count 6 t:FD*
select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8 select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8
@ -32,6 +33,7 @@ endmodule
EOT EOT
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt design -load postopt
select -assert-count 4 t:FD*
select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8 select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8
@ -54,6 +56,6 @@ logger -expect warning "Module 'FDSE' contains a \$_DFF_P_ cell .*" 1
logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1 logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt design -load postopt
#select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8 select -assert-count 8 t:FD*
logger -expect-no-warnings logger -expect-no-warnings