mirror of https://github.com/YosysHQ/yosys.git
Added "verific" command
This commit is contained in:
Clifford Wolf
parent
fcae92868d
commit
8d06f9f2fe
14
Makefile
14
Makefile
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@ -8,6 +8,7 @@ ENABLE_TCL := 1
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ENABLE_QT4 := 1
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ENABLE_MINISAT := 1
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ENABLE_ABC := 1
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ENABLE_VERIFIC := 0
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# other configuration flags
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ENABLE_GPROF := 0
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@ -58,8 +59,10 @@ CXXFLAGS += -std=gnu++0x -march=native -O3 -DNDEBUG
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endif
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ifeq ($(ENABLE_TCL),1)
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CXXFLAGS += -I/usr/include/tcl8.5 -DYOSYS_ENABLE_TCL
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LDLIBS += -ltcl8.5
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TCL_VERSION ?= tcl8.5
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TCL_INCLUDE ?= /usr/include/$(TCL_VERSION)
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CXXFLAGS += -I$(TCL_INCLUDE) -DYOSYS_ENABLE_TCL
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LDLIBS += -l$(TCL_VERSION)
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endif
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ifeq ($(ENABLE_GPROF),1)
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@ -75,6 +78,13 @@ ifeq ($(ENABLE_ABC),1)
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TARGETS += yosys-abc
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endif
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ifeq ($(ENABLE_VERIFIC),1)
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VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
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VERIFIC_COMPONENTS ?= verilog vhdl database util containers
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CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -D'VERIFIC_DIR="$(VERIFIC_DIR)"'
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LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS))
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endif
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OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o
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OBJS += libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o
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@ -0,0 +1 @@
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OBJS += frontends/verific/verific.o
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@ -0,0 +1,488 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <unistd.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include <dirent.h>
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#ifdef VERIFIC_DIR
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#include "veri_file.h"
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#include "vhdl_file.h"
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#include "VeriWrite.h"
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#include "DataBase.h"
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#include "Message.h"
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#ifdef VERIFIC_NAMESPACE
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using namespace Verific ;
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#endif
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static void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
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{
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log("VERIFIC-%s [%s] ",
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msg_type == VERIFIC_NONE ? "NONE" :
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msg_type == VERIFIC_ERROR ? "ERROR" :
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msg_type == VERIFIC_WARNING ? "WARNING" :
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msg_type == VERIFIC_IGNORE ? "IGNORE" :
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msg_type == VERIFIC_INFO ? "INFO" :
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msg_type == VERIFIC_COMMENT ? "COMMENT" :
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msg_type == VERIFIC_PROGRAM_ERROR ? "PROGRAM_ERROR" : "UNKNOWN", message_id);
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if (linefile)
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log("%s:%d: ", LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile));
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logv(msg, args);
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log("\n");
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}
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void import_attributes(std::map<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
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{
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MapIter mi;
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Att *attr;
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if (obj->Linefile())
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attributes["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
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// FIXME: Parse numeric attributes
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FOREACH_ATTRIBUTE(obj, mi, attr)
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attributes[RTLIL::escape_id(attr->Key())] = RTLIL::Const(std::string(attr->Value()));
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}
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static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo)
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{
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if (design->modules.count(RTLIL::escape_id(nl->Owner()->Name())))
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log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
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RTLIL::Module *module = new RTLIL::Module;
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module->name = RTLIL::escape_id(nl->Owner()->Name());
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design->modules[module->name] = module;
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log("Importing module %s.\n", RTLIL::id2cstr(module->name));
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std::map<Net*, RTLIL::SigBit> net_map;
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MapIter mi, mi2;
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Port *port;
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PortBus *portbus;
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Net *net;
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NetBus *netbus;
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Instance *inst;
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FOREACH_PORT_OF_NETLIST(nl, mi, port)
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{
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if (port->Bus())
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continue;
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// log(" importing port %s.\n", port->Name());
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = RTLIL::escape_id(port->Name());
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import_attributes(wire->attributes, port);
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module->add(wire);
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if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_IN)
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wire->port_input = true;
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if (port->GetDir() == DIR_INOUT || port->GetDir() == DIR_OUT)
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wire->port_output = true;
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if (port->GetNet()) {
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net = port->GetNet();
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if (net_map.count(net) == 0)
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net_map[net] = wire;
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else if (wire->port_input)
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module->connections.push_back(RTLIL::SigSig(net_map.at(net), wire));
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else
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module->connections.push_back(RTLIL::SigSig(wire, net_map.at(net)));
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}
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}
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FOREACH_PORTBUS_OF_NETLIST(nl, mi, portbus)
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{
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// log(" importing portbus %s.\n", portbus->Name());
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = RTLIL::escape_id(portbus->Name());
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wire->width = portbus->Size();
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wire->start_offset = std::min(portbus->LeftIndex(), portbus->RightIndex());
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import_attributes(wire->attributes, port);
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module->add(wire);
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if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN)
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wire->port_input = true;
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if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_OUT)
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wire->port_output = true;
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for (int i = portbus->LeftIndex();; i += portbus->IsUp() ? +1 : -1) {
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if (portbus->ElementAtIndex(i) && portbus->ElementAtIndex(i)->GetNet()) {
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net = portbus->ElementAtIndex(i)->GetNet();
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RTLIL::SigBit bit(wire, i - wire->start_offset);
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if (net_map.count(net) == 0)
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net_map[net] = bit;
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else if (wire->port_input)
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module->connections.push_back(RTLIL::SigSig(net_map.at(net), bit));
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else
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module->connections.push_back(RTLIL::SigSig(bit, net_map.at(net)));
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}
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if (i == portbus->RightIndex())
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break;
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}
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}
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module->fixup_ports();
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FOREACH_NET_OF_NETLIST(nl, mi, net)
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{
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if (net_map.count(net)) {
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// log(" skipping net %s.\n", net->Name());
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continue;
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}
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if (net->Bus())
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continue;
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// log(" importing net %s.\n", net->Name());
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = RTLIL::escape_id(net->Name());
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while (module->count_id(wire->name))
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wire->name += "_";
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import_attributes(wire->attributes, port);
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module->add(wire);
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if (net_map.count(net) == 0)
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net_map[net] = wire;
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else
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module->connections.push_back(RTLIL::SigSig(wire, net_map.at(net)));
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}
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FOREACH_NETBUS_OF_NETLIST(nl, mi, netbus)
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{
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bool found_new_net = false;
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for (int i = netbus->LeftIndex();; i += netbus->IsUp() ? +1 : -1) {
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net = netbus->ElementAtIndex(i);
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if (net_map.count(net) == 0)
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found_new_net = true;
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if (i == netbus->RightIndex())
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break;
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}
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if (found_new_net)
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{
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// log(" importing netbus %s.\n", netbus->Name());
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->name = RTLIL::escape_id(netbus->Name());
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wire->width = netbus->Size();
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wire->start_offset = std::min(netbus->LeftIndex(), netbus->RightIndex());
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while (module->count_id(wire->name))
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wire->name += "_";
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import_attributes(wire->attributes, port);
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module->add(wire);
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for (int i = netbus->LeftIndex();; i += netbus->IsUp() ? +1 : -1) {
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if (netbus->ElementAtIndex(i)) {
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net = netbus->ElementAtIndex(i);
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RTLIL::SigBit bit(wire, i - wire->start_offset);
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if (net_map.count(net) == 0)
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net_map[net] = bit;
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else
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module->connections.push_back(RTLIL::SigSig(bit, net_map.at(net)));
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}
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if (i == netbus->RightIndex())
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break;
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}
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}
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else
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{
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// log(" skipping netbus %s.\n", netbus->Name());
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}
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}
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FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
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{
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log(" importing cell %s (%s).\n", inst->Name(), inst->View()->Owner()->Name());
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if (inst->Type() == PRIM_PWR) {
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module->connections.push_back(RTLIL::SigSig(net_map.at(inst->GetOutput()), RTLIL::State::S1));
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continue;
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}
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if (inst->Type() == PRIM_GND) {
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module->connections.push_back(RTLIL::SigSig(net_map.at(inst->GetOutput()), RTLIL::State::S0));
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continue;
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}
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if (inst->Type() == PRIM_X) {
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module->connections.push_back(RTLIL::SigSig(net_map.at(inst->GetOutput()), RTLIL::State::Sx));
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continue;
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}
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if (inst->Type() == PRIM_Z) {
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module->connections.push_back(RTLIL::SigSig(net_map.at(inst->GetOutput()), RTLIL::State::Sz));
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continue;
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}
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if (inst->Type() == PRIM_AND || inst->Type() == PRIM_OR || inst->Type() == PRIM_XOR || inst->Type() == PRIM_XNOR) {
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = RTLIL::escape_id(inst->Name());
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cell->type = inst->Type() == PRIM_AND ? "$and" : inst->Type() == PRIM_OR ? "$or" :
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inst->Type() == PRIM_XOR ? "$xor" : "$xnor";
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cell->parameters["\\A_SIGNED"] = 0;
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cell->parameters["\\B_SIGNED"] = 0;
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cell->parameters["\\A_WIDTH"] = 1;
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cell->parameters["\\B_WIDTH"] = 1;
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cell->parameters["\\Y_WIDTH"] = 1;
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cell->connections["\\A"] = net_map.at(inst->GetInput1());
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cell->connections["\\B"] = net_map.at(inst->GetInput2());
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cell->connections["\\Y"] = net_map.at(inst->GetOutput());
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module->add(cell);
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continue;
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}
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if (inst->Type() == PRIM_INV) {
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = RTLIL::escape_id(inst->Name());
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cell->type = "$not";
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cell->parameters["\\A_SIGNED"] = 0;
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cell->parameters["\\A_WIDTH"] = 1;
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cell->parameters["\\Y_WIDTH"] = 1;
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cell->connections["\\A"] = net_map.at(inst->GetInput());
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cell->connections["\\Y"] = net_map.at(inst->GetOutput());
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module->add(cell);
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continue;
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}
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if (inst->Type() == PRIM_MUX) {
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = RTLIL::escape_id(inst->Name());
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cell->type = "$mux";
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cell->parameters["\\WIDTH"] = 1;
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cell->connections["\\A"] = net_map.at(inst->GetInput1());
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cell->connections["\\B"] = net_map.at(inst->GetInput2());
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cell->connections["\\S"] = net_map.at(inst->GetControl());
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cell->connections["\\Y"] = net_map.at(inst->GetOutput());
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module->add(cell);
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continue;
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}
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if (inst->Type() == PRIM_FADD)
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{
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RTLIL::Cell *cell1 = new RTLIL::Cell;
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cell1->name = RTLIL::escape_id(NEW_ID);
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cell1->type = "$add";
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cell1->parameters["\\A_SIGNED"] = 0;
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cell1->parameters["\\B_SIGNED"] = 0;
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cell1->parameters["\\A_WIDTH"] = 1;
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cell1->parameters["\\B_WIDTH"] = 1;
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cell1->parameters["\\Y_WIDTH"] = 2;
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cell1->connections["\\A"] = net_map.at(inst->GetInput1());
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cell1->connections["\\B"] = net_map.at(inst->GetInput2());
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cell1->connections["\\Y"] = module->new_wire(2, NEW_ID);
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module->add(cell1);
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RTLIL::Cell *cell2 = new RTLIL::Cell;
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cell2->name = RTLIL::escape_id(inst->Name());
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cell2->type = "$add";
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cell2->parameters["\\A_SIGNED"] = 0;
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cell2->parameters["\\B_SIGNED"] = 0;
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cell2->parameters["\\A_WIDTH"] = 2;
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cell2->parameters["\\B_WIDTH"] = 1;
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cell2->parameters["\\Y_WIDTH"] = 2;
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cell2->connections["\\A"] = cell1->connections["\\Y"];
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cell2->connections["\\B"] = net_map.at(inst->GetCin());
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cell2->connections["\\Y"] = net_map.at(inst->GetOutput());
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cell2->connections["\\Y"].append(net_map.at(inst->GetCout()));
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module->add(cell2);
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continue;
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}
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if (inst->IsPrimitive())
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log_error("Unsupported Verific primitive: %s\n", inst->View()->Owner()->Name());
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nl_todo.insert(inst->View());
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = RTLIL::escape_id(inst->Name());
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cell->type = RTLIL::escape_id(inst->View()->Owner()->Name());
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module->add(cell);
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PortRef *pr ;
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FOREACH_PORTREF_OF_INST(inst, mi2, pr) {
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// log(" .%s(%s)\n", pr->GetPort()->Name(), pr->GetNet()->Name());
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const char *port_name = pr->GetPort()->Name();
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int port_offset = 0;
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if (pr->GetPort()->Bus()) {
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port_name = pr->GetPort()->Bus()->Name();
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port_offset = pr->GetPort()->Bus()->IndexOf(pr->GetPort()) -
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std::min(pr->GetPort()->Bus()->LeftIndex(), pr->GetPort()->Bus()->RightIndex());
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}
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RTLIL::SigSpec &conn = cell->connections[RTLIL::escape_id(port_name)];
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while (conn.width <= port_offset)
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conn.append(RTLIL::State::Sz);
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conn.replace(port_offset, net_map.at(pr->GetNet()));
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}
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}
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}
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#endif /* VERIFIC_DIR */
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struct VerificPass : public Pass {
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VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..\n");
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log("\n");
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log("Load the specified Verilog/SystemVerilog files into Verific.\n");
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log("\n");
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log("\n");
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log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..\n");
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log("\n");
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log("Load the specified VHDL files into Verific.\n");
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log("\n");
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log("\n");
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log(" verific -import <top-module>..\n");
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log("\n");
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log("Elaborate the design for the sepcified top modules, import to Yosys and\n");
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log("reset the internal state of Verific.\n");
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log("\n");
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log("\n");
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log("Visit http://verific.com/ for more information on Verific.\n");
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log("\n");
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}
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#ifdef VERIFIC_DIR
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing VERIFIC (loading Verilog and VHDL designs using the Verific library).\n");
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Message::SetConsoleOutput(0);
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Message::RegisterCallBackMsg(msg_func);
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if (args.size() > 1 && args[1] == "-vlog95") {
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for (size_t argidx = 2; argidx < args.size(); argidx++)
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||||
if (!veri_file::Analyze(args[argidx].c_str(), veri_file::VERILOG_95))
|
||||
log_cmd_error("Reading `%s' in VERILOG_95 mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-vlog2k") {
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!veri_file::Analyze(args[argidx].c_str(), veri_file::VERILOG_2K))
|
||||
log_cmd_error("Reading `%s' in VERILOG_2K mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-sv2005") {
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG_2005))
|
||||
log_cmd_error("Reading `%s' in SYSTEM_VERILOG_2005 mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-sv2009") {
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG_2009))
|
||||
log_cmd_error("Reading `%s' in SYSTEM_VERILOG_2009 mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-sv") {
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!veri_file::Analyze(args[argidx].c_str(), veri_file::SYSTEM_VERILOG))
|
||||
log_cmd_error("Reading `%s' in SYSTEM_VERILOG mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-vhdl87") {
|
||||
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87))
|
||||
log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-vhdl93") {
|
||||
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93))
|
||||
log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-vhdl2k") {
|
||||
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K))
|
||||
log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-vhdl2008") {
|
||||
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs");
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++)
|
||||
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008))
|
||||
log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (args.size() > 1 && args[1] == "-import")
|
||||
{
|
||||
std::set<Netlist*> nl_todo, nl_done;
|
||||
|
||||
if (args.size() == 2)
|
||||
log_cmd_error("No top module specified.\n");
|
||||
|
||||
for (size_t argidx = 2; argidx < args.size(); argidx++) {
|
||||
if (veri_file::GetModule(args[argidx].c_str())) {
|
||||
if (!veri_file::Elaborate(args[argidx].c_str()))
|
||||
log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
|
||||
nl_todo.insert(Netlist::PresentDesign());
|
||||
} else {
|
||||
if (!vhdl_file::Elaborate(args[argidx].c_str()))
|
||||
log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
|
||||
nl_todo.insert(Netlist::PresentDesign());
|
||||
}
|
||||
}
|
||||
|
||||
while (!nl_todo.empty()) {
|
||||
Netlist *nl = *nl_todo.begin();
|
||||
if (nl_done.count(nl) == 0)
|
||||
import_netlist(design, nl, nl_todo);
|
||||
nl_todo.erase(nl);
|
||||
nl_done.insert(nl);
|
||||
}
|
||||
|
||||
Libset::Reset();
|
||||
return;
|
||||
}
|
||||
|
||||
log_cmd_error("Missing or unsupported mode parameter.\n");
|
||||
}
|
||||
#else /* VERIFIC_DIR */
|
||||
virtual void execute(std::vector<std::string>, RTLIL::Design *) {
|
||||
log_cmd_error("This version of Yosys is built without Verific support.\n");
|
||||
}
|
||||
#endif
|
||||
} VerificPass;
|
||||
|
||||
Loading…
Reference in New Issue