diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 2d264a6d1..cff4c5ddb 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -287,9 +287,9 @@ struct Ice40DspPass : public Pass {
 		log("cells into iCE40 DSP resources.\n");
 		log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
 		log("\n");
-		log("Pack input registers (A, B, {C,D}; with optional hold/reset), pipeline registers\n");
-		log("({F,J,K,G}, H; with shared reset), output registers (O; with optional hold/reset),\n");
-		log("and post-adder into the SB_MAC16 resource.\n");
+		log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
+		log("({F,J,K,G}, H), output registers (O; with optional hold), and post-adder into\n");
+		log("into the SB_MAC16 resource.\n");
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
 		log("input will be folded into the DSP. In this scenario only, resetting the\n");
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 09fd8406d..b4bfdce4a 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -384,6 +384,8 @@ code argQ argD
 endcode
 
 match ffrstmux
+	if false /* TODO: ice40 resets are actually async */
+
 	if !argD.empty()
 	select ffrstmux->type.in($mux)
 	index <SigSpec> port(ffrstmux, \Y) === argD
@@ -487,6 +489,8 @@ code argD argQ
 endcode
 
 match ffrstmux
+	if false /* TODO: ice40 resets are actually async */
+
 	select ffrstmux->type.in($mux)
 	// ffrstmux output must have two users: ffrstmux and ff.D
 	select nusers(port(ffrstmux, \Y)) == 2