Merge pull request #1699 from YosysHQ/eddie/fix_iopad_init

iopadmap: move \init attributes from outpad output to its input

passes/techmap/iopadmap.cc

@@ -423,6 +423,15 @@ struct IopadmapPass : public Pass {
 					}
 				}
 
+				if (wire->port_output) {
+					auto jt = new_wire->attributes.find(ID(init));
+					// For output ports, move \init attributes from old wire to new wire
+					if (jt != new_wire->attributes.end()) {
+						wire->attributes[ID(init)] = std::move(jt->second);
+						new_wire->attributes.erase(jt);
+					}
+				}
+
 				wire->port_id = 0;
 				wire->port_input = false;
 				wire->port_output = false;

tests/techmap/iopadmap.ys

@@ -120,3 +120,40 @@ select -assert-count 1 g/t:iobuf
 select -assert-count 1 h/t:ibuf
 select -assert-count 1 h/t:iobuf
 select -assert-count 1 h/t:obuf
+
+
+# Check that \init attributes get moved from output buffer
+#   to buffer input
+design -reset
+read_verilog << EOT
+module obuf (input i, (* iopad_external_pin *) output o); endmodule
+module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule
+module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule
+module sub(input i, output o); endmodule
+
+module a(input i, (* init=1'b1 *) output o);
+sub s(.i(i), .o(o));
+endmodule
+
+module b(input [1:0] i, oe, (* init=2'b1x *) output [1:0] o);
+wire [1:0] w;
+sub s1(.i(i[0]), .o(w[0]));
+sub s2(.i(i[1]), .o(w[1]));
+assign o = oe ? w : 2'bz;
+endmodule
+
+module c(input i, oe, (* init=2'b00 *) inout io, output o1, o2);
+assign io = oe ? i : 1'bz;
+assign {o1,o2} = {io,io};
+endmodule
+EOT
+opt_clean
+tribuf
+simplemap
+iopadmap -bits -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io
+select -assert-count 1 a/c:s %co a/a:init=1'b1 %i
+select -assert-count 1 a/a:init
+select -assert-count 1 b/c:s* %co %a b/a:init=2'b1x %i
+select -assert-count 1 b/a:init
+select -assert-count 1 c/t:iobuf %co c/a:init=2'b00 %i
+select -assert-count 1 c/a:init