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Move signal declarations to before first use 

Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
This commit is contained in:
Jeff Goeders 2020-10-19 16:09:04 -06:00
parent 1b7ed719a5
commit 8be56960a2
1 changed files with 2 additions and 2 deletions
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4
techlibs/xilinx/cells_sim.v
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@ -2335,6 +2335,8 @@ parameter integer PREG = 1;
// The multiplier. // The multiplier.
wire signed [35:0] P_MULT; wire signed [35:0] P_MULT;
wire signed [17:0] A_MULT;
wire signed [17:0] B_MULT;
assign P_MULT = A_MULT * B_MULT; assign P_MULT = A_MULT * B_MULT;
// The cascade output. // The cascade output.
@ -2373,8 +2375,6 @@ always @(posedge CLK) begin
end end
// The register enables. // The register enables.
wire signed [17:0] A_MULT;
wire signed [17:0] B_MULT;
assign A_MULT = (AREG == 1) ? A_REG : A; assign A_MULT = (AREG == 1) ? A_REG : A;
assign B_MULT = (BREG == 1) ? B_REG : B_MUX; assign B_MULT = (BREG == 1) ? B_REG : B_MUX;
assign P = (PREG == 1) ? P_REG : P_MULT; assign P = (PREG == 1) ? P_REG : P_MULT;