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Detect illegal port declaration, e.g input/output/inout keyword must be the first.

This commit is contained in:
Udi Finkelstein 2018-06-06 22:27:25 +03:00
parent 270c1814b5
commit 8b7580b0a1
1 changed files with 6 additions and 3 deletions
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9
frontends/verilog/verilog_parser.y
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@ -376,9 +376,10 @@ wire_type:
}; };
wire_type_token_list: wire_type_token_list:
wire_type_token | wire_type_token_list wire_type_token; wire_type_token | wire_type_token_list wire_type_token |
wire_type_token_io ;
wire_type_token: wire_type_token_io:
TOK_INPUT { TOK_INPUT {
astbuf3->is_input = true; astbuf3->is_input = true;
} | } |
@ -388,7 +389,9 @@ wire_type_token:
TOK_INOUT { TOK_INOUT {
astbuf3->is_input = true; astbuf3->is_input = true;
astbuf3->is_output = true; astbuf3->is_output = true;
} | };
wire_type_token:
TOK_WIRE { TOK_WIRE {
} | } |
TOK_REG { TOK_REG {