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Merge pull request #3796 from YosysHQ/micko/update_abc 

Update ABC to latest
This commit is contained in:
Miodrag Milanović 2023-06-12 16:06:56 +02:00 committed by GitHub
parent 236e15f3b0 e6f7cf3b29
commit 8b74e8ad3a
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GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 20 additions and 18 deletions
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2
Makefile
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@ -165,7 +165,7 @@ bumpversion:
# is just a symlink to your actual ABC working directory, as 'make mrproper' # is just a symlink to your actual ABC working directory, as 'make mrproper'
# will remove the 'abc' directory and you do not want to accidentally # will remove the 'abc' directory and you do not want to accidentally
# delete your work on ABC.. # delete your work on ABC..
ABCREV = 2c1c83f ABCREV = 1de4eaf
ABCPULL = 1 ABCPULL = 1
ABCURL ?= https://github.com/YosysHQ/abc ABCURL ?= https://github.com/YosysHQ/abc
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)

8
tests/arch/anlogic/mux.ys
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@ -26,10 +26,12 @@ proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 3 t:AL_MAP_LUT4 select -assert-max 3 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_LUT6 select -assert-max 3 t:AL_MAP_LUT4
select -assert-max 1 t:AL_MAP_LUT5
select -assert-max 1 t:AL_MAP_LUT6
select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D
design -load read design -load read
hierarchy -top mux16 hierarchy -top mux16

4
tests/arch/ecp5/mux.ys
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@ -28,8 +28,8 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-max 1 t:L6MUX21 select -assert-max 1 t:L6MUX21
select -assert-max 7 t:LUT4 select -assert-max 8 t:LUT4
select -assert-max 2 t:PFUMX select -assert-max 3 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D

2
tests/arch/gatemate/fsm.ys
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@ -15,6 +15,6 @@ cd fsm # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG select -assert-count 1 t:CC_BUFG
select -assert-count 6 t:CC_DFF select -assert-count 6 t:CC_DFF
select -assert-max 5 t:CC_LUT2 select -assert-max 5 t:CC_LUT2
select -assert-max 4 t:CC_LUT3 select -assert-max 6 t:CC_LUT3
select -assert-max 9 t:CC_LUT4 select -assert-max 9 t:CC_LUT4
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D

2
tests/arch/ice40/rom.ys
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@ -4,5 +4,5 @@ flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 5 t:SB_LUT4 select -assert-max 6 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D select -assert-none t:SB_LUT4 %% t:* %D

8
tests/arch/intel_alm/mux.ys
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@ -69,7 +69,7 @@ proc
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT3 select -assert-max 1 t:MISTRAL_ALUT3
select -assert-max 2 t:MISTRAL_ALUT5 select -assert-max 2 t:MISTRAL_ALUT5
select -assert-max 5 t:MISTRAL_ALUT6 select -assert-max 5 t:MISTRAL_ALUT6
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D
@ -81,8 +81,8 @@ proc
equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT3 select -assert-max 1 t:MISTRAL_ALUT3
select -assert-count 2 t:MISTRAL_ALUT5 select -assert-max 2 t:MISTRAL_ALUT5
select -assert-count 4 t:MISTRAL_ALUT6 select -assert-max 5 t:MISTRAL_ALUT6
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D

3
tests/arch/nexus/mux.ys
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@ -36,8 +36,7 @@ proc
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module cd mux16 # Constrain all select calls below inside the top module
select -assert-min 11 t:LUT4
select -assert-max 12 t:LUT4 select -assert-max 12 t:LUT4
select -assert-count 1 t:WIDEFN9 select -assert-max 2 t:WIDEFN9
select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D

9
tests/arch/xilinx/mux_lut4.ys
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@ -30,12 +30,13 @@ proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module cd mux8 # Constrain all select calls below inside the top module
select -assert-count 4 t:LUT1 select -assert-max 5 t:LUT1
select -assert-count 3 t:LUT4 select -assert-max 3 t:LUT3
select -assert-count 2 t:MUXF5 select -assert-max 3 t:LUT4
select -assert-max 3 t:MUXF5
select -assert-count 1 t:MUXF6 select -assert-count 1 t:MUXF6
select -assert-none t:LUT1 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D
design -load read design -load read