From b623888f6aa3b9d519cdb55bc7508021ae43dad2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 6 Jun 2023 11:57:20 +0200 Subject: [PATCH 1/3] Update ABC to latest --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6732998af..f957c7730 100644 --- a/Makefile +++ b/Makefile @@ -165,7 +165,7 @@ bumpversion: # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 2c1c83f +ABCREV = 0b36135 ABCPULL = 1 ABCURL ?= https://github.com/YosysHQ/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From 0d4a67026732749931463c7f455f72c8e21d110c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 6 Jun 2023 14:37:14 +0200 Subject: [PATCH 2/3] Update ABC --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f957c7730..a5049bfa4 100644 --- a/Makefile +++ b/Makefile @@ -165,7 +165,7 @@ bumpversion: # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 0b36135 +ABCREV = 1de4eaf ABCPULL = 1 ABCURL ?= https://github.com/YosysHQ/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) From e6f7cf3b29adcfef592055158308c6ab2bc69288 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 9 Jun 2023 14:41:45 +0200 Subject: [PATCH 3/3] Update tests --- tests/arch/anlogic/mux.ys | 8 +++++--- tests/arch/ecp5/mux.ys | 4 ++-- tests/arch/gatemate/fsm.ys | 2 +- tests/arch/ice40/rom.ys | 2 +- tests/arch/intel_alm/mux.ys | 8 ++++---- tests/arch/nexus/mux.ys | 3 +-- tests/arch/xilinx/mux_lut4.ys | 9 +++++---- 7 files changed, 19 insertions(+), 17 deletions(-) diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys index 3d5fe7c9a..89014b5e0 100644 --- a/tests/arch/anlogic/mux.ys +++ b/tests/arch/anlogic/mux.ys @@ -26,10 +26,12 @@ proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 3 t:AL_MAP_LUT4 -select -assert-count 1 t:AL_MAP_LUT6 +select -assert-max 3 t:AL_MAP_LUT3 +select -assert-max 3 t:AL_MAP_LUT4 +select -assert-max 1 t:AL_MAP_LUT5 +select -assert-max 1 t:AL_MAP_LUT6 -select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D design -load read hierarchy -top mux16 diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index db63dda5f..daa9e86f2 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -28,8 +28,8 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-max 1 t:L6MUX21 -select -assert-max 7 t:LUT4 -select -assert-max 2 t:PFUMX +select -assert-max 8 t:LUT4 +select -assert-max 3 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys index 6b43ead7a..506862c90 100644 --- a/tests/arch/gatemate/fsm.ys +++ b/tests/arch/gatemate/fsm.ys @@ -15,6 +15,6 @@ cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:CC_BUFG select -assert-count 6 t:CC_DFF select -assert-max 5 t:CC_LUT2 -select -assert-max 4 t:CC_LUT3 +select -assert-max 6 t:CC_LUT3 select -assert-max 9 t:CC_LUT4 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D diff --git a/tests/arch/ice40/rom.ys b/tests/arch/ice40/rom.ys index 41d214e2a..d795e206b 100644 --- a/tests/arch/ice40/rom.ys +++ b/tests/arch/ice40/rom.ys @@ -4,5 +4,5 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 5 t:SB_LUT4 +select -assert-max 6 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/intel_alm/mux.ys b/tests/arch/intel_alm/mux.ys index 6fb6ae80a..20969ead3 100644 --- a/tests/arch/intel_alm/mux.ys +++ b/tests/arch/intel_alm/mux.ys @@ -69,7 +69,7 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 +select -assert-max 1 t:MISTRAL_ALUT3 select -assert-max 2 t:MISTRAL_ALUT5 select -assert-max 5 t:MISTRAL_ALUT6 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D @@ -81,8 +81,8 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-count 2 t:MISTRAL_ALUT5 -select -assert-count 4 t:MISTRAL_ALUT6 +select -assert-max 1 t:MISTRAL_ALUT3 +select -assert-max 2 t:MISTRAL_ALUT5 +select -assert-max 5 t:MISTRAL_ALUT6 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D diff --git a/tests/arch/nexus/mux.ys b/tests/arch/nexus/mux.ys index 0e12d674a..280d3e48f 100644 --- a/tests/arch/nexus/mux.ys +++ b/tests/arch/nexus/mux.ys @@ -36,8 +36,7 @@ proc equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-min 11 t:LUT4 select -assert-max 12 t:LUT4 -select -assert-count 1 t:WIDEFN9 +select -assert-max 2 t:WIDEFN9 select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D diff --git a/tests/arch/xilinx/mux_lut4.ys b/tests/arch/xilinx/mux_lut4.ys index 3e3256993..147601dce 100644 --- a/tests/arch/xilinx/mux_lut4.ys +++ b/tests/arch/xilinx/mux_lut4.ys @@ -30,12 +30,13 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc3se -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 4 t:LUT1 -select -assert-count 3 t:LUT4 -select -assert-count 2 t:MUXF5 +select -assert-max 5 t:LUT1 +select -assert-max 3 t:LUT3 +select -assert-max 3 t:LUT4 +select -assert-max 3 t:MUXF5 select -assert-count 1 t:MUXF6 -select -assert-none t:LUT1 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D +select -assert-none t:LUT1 t:LUT3 t:LUT4 t:MUXF5 t:MUXF6 %% t:* %D design -load read