riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Updated TODO section in README

This commit is contained in:
Clifford Wolf 2013-08-01 20:02:15 +02:00
parent 0f38008ed3
commit 8b2f7792ba
1 changed files with 1 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
README
View File

@ -238,14 +238,6 @@ Verilog Attributes and non-standard features
TODOs / Open Bugs TODOs / Open Bugs
================= =================
- Write "design and implementation of.." document
- Source tree layout
- Data formats (c++ classes, etc.)
- Internal misc. frameworks (log, select)
- Build system and pass registration
- Internal cell library
- Implement missing Verilog 2005 features: - Implement missing Verilog 2005 features:
- Signed constants - Signed constants
@ -264,7 +256,7 @@ TODOs / Open Bugs
- Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
- Add edit commands for changing the design (delete, add, modify objects) - Add edit commands for changing the design (delete, add, modify objects)
- Improve TCL support (add mechanism for inspecting the design from TCL) - Improve TCL support (add mechanism for inspecting the design from TCL)
- Additional internal cell types: $pla and $lut - Add full support for $lut cell type (const evaluation, sat solving, etc.)
- Support for registering designs (as collection of modules) to CellTypes - Support for registering designs (as collection of modules) to CellTypes
- Smarter resource sharing pass (add MUXes and get rid of duplicated cells) - Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
- Refactoring of AST frontend (clean expr width/sign code, AST passes) - Refactoring of AST frontend (clean expr width/sign code, AST passes)