mirror of https://github.com/YosysHQ/yosys.git
Add techlibs/xilinx/lut2lut.v
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@ -29,6 +29,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
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$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
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$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
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@ -0,0 +1,65 @@
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module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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\$lut #(
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.WIDTH(1),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A(I0),
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.Y(O)
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);
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endmodule
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module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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\$lut #(
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.WIDTH(2),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT3(output O, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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\$lut #(
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.WIDTH(3),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I2, I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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\$lut #(
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.WIDTH(4),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I3, I2, I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT5(output O, input I0, I1, I2, I3, I4);
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parameter [31:0] INIT = 0;
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\$lut #(
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.WIDTH(5),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I4, I3, I2, I1, I0}),
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.Y(O)
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);
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endmodule
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module LUT6(output O, input I0, I1, I2, I3, I4, I5);
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parameter [63:0] INIT = 0;
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\$lut #(
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.WIDTH(6),
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.LUT(INIT)
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) _TECHMAP_REPLACE_ (
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.A({I5, I4, I3, I2, I1, I0}),
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.Y(O)
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);
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endmodule
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