riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER

This commit is contained in:
Eddie Hung 2019-08-12 12:19:25 -07:00
parent 12c692f6ed
commit 8a2480526f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
techlibs/ice40/cells_map.v
View File

@ -75,7 +75,7 @@ module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
.WIDTH(4), .WIDTH(4),
.LUT(LUT) .LUT(LUT)
) lut ( ) lut (
.A({I3,B,A,I0}), .A({I0,A,B,I3}),
.Y(O) .Y(O)
); );
endmodule endmodule