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select.cc: Fixes for selections

This commit is contained in:
Krystine Sherwin 2024-11-25 17:18:21 +13:00
parent 08e849a651
commit 89c5ff0a39
No known key found for this signature in database
1 changed files with 29 additions and 40 deletions
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69
passes/cmds/select.cc
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@ -212,21 +212,16 @@ static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int c
{ {
vector<pair<IdString, IdString>> objects; vector<pair<IdString, IdString>> objects;
for (auto mod : design->modules()) design->push_selection(lhs);
for (auto mod : design->all_selected_modules())
{ {
if (!lhs.selected_module(mod->name)) for (auto cell : mod->selected_cells())
continue; objects.push_back(make_pair(mod->name, cell->name));
for (auto cell : mod->cells()) { for (auto wire : mod->selected_wires())
if (lhs.selected_member(mod->name, cell->name)) objects.push_back(make_pair(mod->name, wire->name));
objects.push_back(make_pair(mod->name, cell->name));
}
for (auto wire : mod->wires()) {
if (lhs.selected_member(mod->name, wire->name))
objects.push_back(make_pair(mod->name, wire->name));
}
} }
design->pop_selection();
lhs = RTLIL::Selection(false, lhs.selects_boxes, design); lhs = RTLIL::Selection(false, lhs.selects_boxes, design);
@ -243,28 +238,23 @@ static void select_op_random(RTLIL::Design *design, RTLIL::Selection &lhs, int c
static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
{ {
for (auto mod : design->modules()) design->push_selection(lhs);
{ for (auto mod : design->all_selected_modules())
if (lhs.selected_whole_module(mod->name)) for (auto cell : mod->selected_cells())
{ if (design->module(cell->type) != nullptr)
for (auto cell : mod->cells())
{
if (design->module(cell->type) == nullptr)
continue;
lhs.selected_modules.insert(cell->type); lhs.selected_modules.insert(cell->type);
} design->pop_selection();
}
}
} }
static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_cells_to_modules(RTLIL::Design *design, RTLIL::Selection &lhs)
{ {
RTLIL::Selection new_sel(false, lhs.selects_boxes, design); RTLIL::Selection new_sel(false, lhs.selects_boxes, design);
for (auto mod : design->modules()) design->push_selection(lhs);
if (lhs.selected_module(mod->name)) for (auto mod : design->all_selected_modules())
for (auto cell : mod->cells()) for (auto cell : mod->selected_cells())
if (lhs.selected_member(mod->name, cell->name) && (design->module(cell->type) != nullptr)) if (design->module(cell->type) != nullptr)
new_sel.selected_modules.insert(cell->type); new_sel.selected_modules.insert(cell->type);
design->pop_selection();
lhs = new_sel; lhs = new_sel;
} }
@ -288,26 +278,23 @@ static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs)
static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
{ {
for (auto mod : design->modules()) design->push_selection(lhs);
for (auto mod : design->all_selected_modules())
{ {
if (!lhs.selects_boxes && mod->get_blackbox_attribute())
continue;
if (lhs.selected_whole_module(mod->name)) if (lhs.selected_whole_module(mod->name))
continue; continue;
if (!lhs.selected_module(mod->name))
continue;
SigMap sigmap(mod); SigMap sigmap(mod);
SigPool selected_bits; SigPool selected_bits;
for (auto wire : mod->wires()) for (auto wire : mod->selected_wires())
if (lhs.selected_member(mod->name, wire->name)) selected_bits.add(sigmap(wire));
selected_bits.add(sigmap(wire));
for (auto wire : mod->wires()) for (auto wire : mod->wires())
if (!lhs.selected_member(mod->name, wire->name) && selected_bits.check_any(sigmap(wire))) if (!lhs.selected_member(mod->name, wire->name) && selected_bits.check_any(sigmap(wire)))
lhs.selected_members[mod->name].insert(wire->name); lhs.selected_members[mod->name].insert(wire->name);
} }
design->pop_selection();
} }
static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs) static void select_op_union(RTLIL::Design* design, RTLIL::Selection &lhs, const RTLIL::Selection &rhs)
@ -476,16 +463,17 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
{ {
int sel_objects = 0; int sel_objects = 0;
bool is_input, is_output; bool is_input, is_output;
for (auto mod : design->modules()) design->push_selection(lhs);
for (auto mod : design->all_selected_modules())
{ {
if (lhs.selected_whole_module(mod->name) || !lhs.selected_module(mod->name)) if (lhs.is_selected_whole_module(mod->name))
continue; continue;
std::set<RTLIL::Wire*> selected_wires; std::set<RTLIL::Wire*> selected_wires;
auto selected_members = lhs.selected_members[mod->name]; auto selected_members = lhs.selected_members[mod->name];
for (auto wire : mod->wires()) for (auto wire : mod->selected_wires())
if (lhs.selected_member(mod->name, wire->name) && limits.count(wire->name) == 0) if (limits.count(wire->name) == 0)
selected_wires.insert(wire); selected_wires.insert(wire);
for (auto &conn : mod->connections()) for (auto &conn : mod->connections())
@ -537,6 +525,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
exclude_match:; exclude_match:;
} }
} }
design->pop_selection();
return sel_objects; return sel_objects;
} }