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Vivado does not like zero width port connections

This commit is contained in:
Eddie Hung 2019-09-23 19:04:07 -07:00
parent 67c2db3486
commit 895e2befa7
1 changed files with 2 additions and 2 deletions
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4
techlibs/xilinx/xilinx_finalise.cc
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@ -53,7 +53,7 @@ struct XilinxFinalisePass : public Pass
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
if (cell->type != ID(DSP48E1)) if (cell->type != ID(DSP48E1))
continue; continue;
for (auto &conn : cell->connections_) { for (auto conn : cell->connections()) {
if (!cell->output(conn.first)) if (!cell->output(conn.first))
continue; continue;
bool purge = true; bool purge = true;
@ -74,7 +74,7 @@ struct XilinxFinalisePass : public Pass
if (purge) { if (purge) {
log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second)); log_debug("Purging unused port connection %s %s (.%s(%s))\n", cell->type.c_str(), log_id(cell), log_id(conn.first), log_signal(conn.second));
conn.second = SigSpec(); cell->unsetPort(conn.first);
} }
} }
} }