mirror of https://github.com/YosysHQ/yosys.git
Restore count_outputs, move process check to abc
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@ -164,7 +164,7 @@ struct Abc9Pass : public ScriptPass
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map_cmd << " " << arg << " " << args[++argidx];
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map_cmd << " " << arg << " " << args[++argidx];
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continue;
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continue;
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}
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}
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if (arg == "-fast" || /*arg == "-dff" ||*/ arg == "-keepff"
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if (arg == "-fast"
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/*|| arg == "-nocleanup"*/ || arg == "-showtmp" || arg == "-markgroups"
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/*|| arg == "-nocleanup"*/ || arg == "-showtmp" || arg == "-markgroups"
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|| arg == "-nomfs") {
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|| arg == "-nomfs") {
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map_cmd << " " << arg;
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map_cmd << " " << arg;
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@ -189,6 +189,14 @@ struct Abc9Pass : public ScriptPass
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active_design->selection_stack.emplace_back(false);
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active_design->selection_stack.emplace_back(false);
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for (auto mod : selected_modules) {
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for (auto mod : selected_modules) {
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if (module->attributes.count(ID(abc9_box_id)))
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continue;
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(module));
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continue;
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}
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log_push();
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log_push();
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active_design->selection().select(mod);
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active_design->selection().select(mod);
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@ -268,15 +268,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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log_push();
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log_push();
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// FIXME:
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int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs");
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/*int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs");
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log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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design->scratchpad_get_int("write_xaiger.num_ands"),
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design->scratchpad_get_int("write_xaiger.num_ands"),
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design->scratchpad_get_int("write_xaiger.num_wires"),
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design->scratchpad_get_int("write_xaiger.num_wires"),
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design->scratchpad_get_int("write_xaiger.num_inputs"),
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design->scratchpad_get_int("write_xaiger.num_inputs"),
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count_outputs);
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count_outputs);
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if (count_outputs > 0)*/ {
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if (count_outputs > 0) {
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std::string buffer;
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std::string buffer;
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std::ifstream ifs;
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std::ifstream ifs;
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#if 0
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#if 0
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@ -965,13 +964,8 @@ struct Abc9MapPass : public Pass {
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CellTypes ct(design);
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CellTypes ct(design);
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for (auto module : design->selected_modules())
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for (auto module : design->selected_modules())
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{
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{
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if (module->attributes.count(ID(abc9_box_id)))
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if (module->processes.size() > 0)
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continue;
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log_error("Module '%s' has processes!\n", log_id(module));
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(module));
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continue;
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}
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assign_map.set(module);
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assign_map.set(module);
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