mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4790 from YosysHQ/emil/clockgate-warnings
clockgate: reduce build warnings
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commit
889894a6d2
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@ -106,28 +106,28 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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if (pin->id != "pin" || pin->args.size() != 1)
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continue;
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if (auto clk = pin->find("clock_gate_clock_pin")) {
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if (pin->find("clock_gate_clock_pin")) {
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if (!icg_interface.clk_in_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto gclk = pin->find("clock_gate_out_pin")) {
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} else if (pin->find("clock_gate_out_pin")) {
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if (!icg_interface.clk_out_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto en = pin->find("clock_gate_enable_pin")) {
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} else if (pin->find("clock_gate_enable_pin")) {
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if (!icg_interface.ce_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
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cell_name.c_str());
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continue;
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} else
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icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto se = pin->find("clock_gate_test_pin")) {
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} else if (pin->find("clock_gate_test_pin")) {
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icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0]));
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} else {
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const LibertyAst *dir = pin->find("direction");
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