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Merge pull request #4790 from YosysHQ/emil/clockgate-warnings 

clockgate: reduce build warnings
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KrystalDelusion 2024-12-03 13:25:52 +13:00 committed by GitHub
parent a8a65db0bc 6b006e5f61
commit 889894a6d2
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GPG Key ID: B5690EEEBB952194
1 changed files with 4 additions and 4 deletions
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8
passes/techmap/clockgate.cc
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@ -106,28 +106,28 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
if (pin->id != "pin" || pin->args.size() != 1) if (pin->id != "pin" || pin->args.size() != 1)
continue; continue;
if (auto clk = pin->find("clock_gate_clock_pin")) { if (pin->find("clock_gate_clock_pin")) {
if (!icg_interface.clk_in_pin.empty()) { if (!icg_interface.clk_in_pin.empty()) {
log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n", log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
cell_name.c_str()); cell_name.c_str());
continue; continue;
} else } else
icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]); icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]);
} else if (auto gclk = pin->find("clock_gate_out_pin")) { } else if (pin->find("clock_gate_out_pin")) {
if (!icg_interface.clk_out_pin.empty()) { if (!icg_interface.clk_out_pin.empty()) {
log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n", log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
cell_name.c_str()); cell_name.c_str());
continue; continue;
} else } else
icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]); icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]);
} else if (auto en = pin->find("clock_gate_enable_pin")) { } else if (pin->find("clock_gate_enable_pin")) {
if (!icg_interface.ce_pin.empty()) { if (!icg_interface.ce_pin.empty()) {
log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n", log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
cell_name.c_str()); cell_name.c_str());
continue; continue;
} else } else
icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]); icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]);
} else if (auto se = pin->find("clock_gate_test_pin")) { } else if (pin->find("clock_gate_test_pin")) {
icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0])); icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0]));
} else { } else {
const LibertyAst *dir = pin->find("direction"); const LibertyAst *dir = pin->find("direction");