Towards Xilinx bram support

passes/memory/memory_bram.cc

@@ -73,20 +73,21 @@ struct rules_t
 	std::ifstream infile;
 	vector<string> tokens;
 	int linecount;
-	string line;
 
 	void syntax_error()
 	{
-		if (line.empty())
+		if (tokens.empty())
 			log_error("Unexpected end of rules file in line %d.\n", linecount);
-		log_error("Syntax error in rules file line %d: %s\n", linecount, line.c_str());
+		log_error("Syntax error in rules file line %d.\n", linecount);
 	}
 
 	bool next_line()
 	{
 		linecount++;
 		tokens.clear();
+		string line;
 		while (std::getline(infile, line)) {
+			log("> %s\n", line.c_str());
 			for (string tok = next_token(line); !tok.empty(); tok = next_token(line)) {
 				if (tok[0] == '#')
 					break;

techlibs/xilinx/Makefile.inc

@@ -1,9 +1,17 @@
 
 OBJS += techlibs/xilinx/synth_xilinx.o
 
-EXTRA_TARGETS += share/xilinx/cells.v
+EXTRA_TARGETS += share/xilinx/cells.v share/xilinx/brams.txt share/xilinx/brams.v
 
 share/xilinx/cells.v: techlibs/xilinx/cells.v
 	$(P) mkdir -p share/xilinx
 	$(Q) cp techlibs/xilinx/cells.v share/xilinx/cells.v
 
+share/xilinx/brams.txt: techlibs/xilinx/brams.txt
+	$(P) mkdir -p share/xilinx
+	$(Q) cp techlibs/xilinx/brams.txt share/xilinx/brams.txt
+
+share/xilinx/brams.v: techlibs/xilinx/brams.v
+	$(P) mkdir -p share/xilinx
+	$(Q) cp techlibs/xilinx/brams.v share/xilinx/brams.v
+

techlibs/xilinx/brams.txt

@@ -1,20 +1,122 @@
 
-# This is a very simplified description of the capabilities of
+bram $__XILINX_RAMB36_SDP72
-# the Xilinx RAMB36 core. But it is a start..
+  abits 9
-#
+  dbits 72
-bram XILINX_RAMB36_SDP32
-  init 1
-  abits 10
-  dbits 32
   groups 2
   ports  1 1
-  wrmode 1 0
+  wrmode 0 1
-  enable 4 0
+  enable 0 8
-  transp 0 2
+  transp 2 0
-  clocks 1 2
+  clocks 2 3
+  clkpol 2 3
 endbram
 
-match XILINX_RAMB36_SDP32
+bram $__XILINX_RAMB36_SDP36
-  min bits 1024
+  abits 10
+  dbits 36
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 4
+  transp 2 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB36_SDP18
+  abits 11
+  dbits 18
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 2
+  transp 2 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB36_SDP9
+  abits 12
+  dbits 9
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 2 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB36_SDP4
+  abits 13
+  dbits 4
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 2 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB36_SDP2
+  abits 14
+  dbits 2
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 2 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+bram $__XILINX_RAMB36_SDP1
+  abits 15
+  dbits 1
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 2 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+match $__XILINX_RAMB36_SDP72
+  shuffle_enable 8
+  min efficiency 20
+  # or_next_if_better
 endmatch
 
+# match $__XILINX_RAMB36_SDP36
+#   shuffle_enable 4
+#   min efficiency 20
+#   or_next_if_better
+# endmatch
+#
+# match $__XILINX_RAMB36_SDP18
+#   shuffle_enable 2
+#   min efficiency 20
+#   or_next_if_better
+# endmatch
+#
+# match $__XILINX_RAMB36_SDP9
+#   min efficiency 20
+#   or_next_if_better
+# endmatch
+#
+# match $__XILINX_RAMB36_SDP4
+#   min efficiency 20
+#   or_next_if_better
+# endmatch
+#
+# match $__XILINX_RAMB36_SDP2
+#   min efficiency 20
+#   or_next_if_better
+# endmatch
+#
+# match $__XILINX_RAMB36_SDP1
+#   min efficiency 20
+# endmatch
+

techlibs/xilinx/brams.v

@@ -0,0 +1,59 @@
+module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter TRANSP2 = 1;
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+
+	input CLK2;
+	input CLK3;
+
+	input [8:0] A1ADDR;
+	output [71:0] A1DATA;
+
+	input [8:0] B1ADDR;
+	input [71:0] B1DATA;
+	input [7:0] B1EN;
+
+	wire [15:0] A1ADDR_16 = A1ADDR;
+	wire [15:0] B1ADDR_16 = B1ADDR;
+
+	wire [7:0] DIP, DOP;
+	wire [63:0] DI, DO;
+
+	assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
+	                  DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+
+	assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
+	         DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+	RAMB36E1 #(
+		.RAM_MODE("SDP"),
+		.READ_WIDTH_A(72),
+		.WRITE_WIDTH_B(72),
+		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+	) _TECHMAP_REPLACE_ (
+		.DOBDO(DO[63:32]),
+		.DOADO(DO[31:0]),
+		.DOPBDOP(DOP[7:4]),
+		.DOPADOP(DOP[3:0]),
+		.DIBDI(DI[63:32]),
+		.DIADI(DI[31:0]),
+		.DIPBDIP(DIP[7:4]),
+		.DIPADIP(DIP[3:0]),
+
+		.ADDRARDADDR(A1ADDR_16),
+		.CLKARDCLK(CLK2 == |CLKPOL2),
+		.ENARDEN(|1),
+		.REGCEAREGCE(|1),
+		.RSTRAMARSTRAM(|0),
+		.RSTREGARSTREG(|0),
+		.WEA(4'b0),
+
+		.ADDRBWRADDR(B1ADDR_16),
+		.CLKBWRCLK(CLK3 == |CLKPOL3),
+		.ENBWREN(|1),
+		.REGCEB(|0),
+		.RSTRAMB(|0),
+		.RSTREGB(|0),
+		.WEBWE(B1EN)
+	);
+endmodule