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Disable shregmap in synth_xilinx if -retime

This commit is contained in:
Eddie Hung 2019-04-03 07:14:20 -07:00
parent f7a0434d54
commit 88630cd02c
1 changed files with 3 additions and 3 deletions
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6
techlibs/xilinx/synth_xilinx.cc
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@ -113,8 +113,8 @@ struct SynthXilinxPass : public Pass
log(" dffsr2dff\n"); log(" dffsr2dff\n");
log(" dff2dffe\n"); log(" dff2dffe\n");
log(" opt -full\n"); log(" opt -full\n");
log(" simplemap t:$dff* (only without -nosrl)\n"); log(" simplemap t:$dff* (without -nosrl and without -retime only)\n");
log(" shregmap -tech xilinx -minlen 3 (only without -nosrl)\n"); log(" shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n");
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
log(" opt -fast\n"); log(" opt -fast\n");
log("\n"); log("\n");
@ -265,7 +265,7 @@ struct SynthXilinxPass : public Pass
Pass::call(design, "dff2dffe"); Pass::call(design, "dff2dffe");
Pass::call(design, "opt -full"); Pass::call(design, "opt -full");
if (!nosrl) { if (!nosrl && !retime) {
Pass::call(design, "simplemap t:$dff*"); Pass::call(design, "simplemap t:$dff*");
Pass::call(design, "shregmap -tech xilinx -minlen 3"); Pass::call(design, "shregmap -tech xilinx -minlen 3");
} }