From a265a846324fc1699e22cad00ff23823464a84ae Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 1 Dec 2019 23:26:17 -0800
Subject: [PATCH 1/2] Use pool instead of std::set for determinism

---
 passes/hierarchy/submod.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 211f96175..3b4f33a60 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -42,7 +42,7 @@ struct SubmodWorker
 	struct SubModule
 	{
 		std::string name, full_name;
-		std::set<RTLIL::Cell*> cells;
+		pool<RTLIL::Cell*> cells;
 	};
 
 	std::map<std::string, SubModule> submodules;

From 705e520a527864dc32f1934bb4b2b94d75f8f0ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 13:14:46 -0800
Subject: [PATCH 2/2] Add a quick testcase for unknown modules as inout

---
 tests/various/submod.ys | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index 9d7dabdd7..4fb45043b 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -80,9 +80,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
 
-
 design -reset
-read_verilog -icells <<EOT
+read_verilog <<EOT
 module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
 (* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
 DFF s2(.D(d), .C(c), .Q(q[0]));
@@ -100,3 +99,26 @@ proc
 submod
 dffinit -ff DFF Q INIT
 check -noinit -assert
+
+
+design -reset
+read_verilog <<EOT
+module top(input d, c, output reg [2:0] q);
+(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
+DFF s2(.D(d), .C(c), .Q(q[0]));
+DFF s3(.D(d), .C(c), .Q(q[2]));
+endmodule
+EOT
+
+hierarchy -top top
+proc
+
+submod
+flatten
+
+read_verilog <<EOT
+module DFF(input D, C, output Q);
+endmodule
+EOT
+
+check -assert