mirror of https://github.com/YosysHQ/yosys.git
Added warning for use of 'z' constants in HDL
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4e5350b409
commit
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@ -132,8 +132,16 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
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}
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}
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// convert the verilog code for a constant to an AST node
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// convert the verilog code for a constant to an AST node
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AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type)
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AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn_z)
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{
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{
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if (warn_z) {
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AstNode *ret = const2ast(code, case_type);
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if (std::find(ret->bits.begin(), ret->bits.end(), RTLIL::State::Sz) != ret->bits.end())
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log_warning("Yosys does not support tri-state logic at the moment. (%s:%d)\n",
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current_filename.c_str(), frontend_verilog_yyget_lineno());
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return ret;
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}
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const char *str = code.c_str();
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const char *str = code.c_str();
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// Strings
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// Strings
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@ -43,7 +43,7 @@ namespace VERILOG_FRONTEND
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extern struct AST::AstNode *current_ast;
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extern struct AST::AstNode *current_ast;
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// this function converts a Verilog constant to an AST_CONSTANT node
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// this function converts a Verilog constant to an AST_CONSTANT node
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AST::AstNode *const2ast(std::string code, char case_type = 0);
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AST::AstNode *const2ast(std::string code, char case_type = 0, bool warn_z = false);
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// state of `default_nettype
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// state of `default_nettype
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extern bool default_nettype_wire;
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extern bool default_nettype_wire;
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@ -1251,7 +1251,7 @@ basic_expr:
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if ($4->substr(0, 1) != "'")
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if ($4->substr(0, 1) != "'")
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frontend_verilog_yyerror("Syntax error.");
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frontend_verilog_yyerror("Syntax error.");
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AstNode *bits = $2;
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AstNode *bits = $2;
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AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
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AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true);
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if (val == NULL)
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if (val == NULL)
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log_error("Value conversion failed: `%s'\n", $4->c_str());
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log_error("Value conversion failed: `%s'\n", $4->c_str());
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$$ = new AstNode(AST_TO_BITS, bits, val);
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$$ = new AstNode(AST_TO_BITS, bits, val);
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@ -1262,7 +1262,7 @@ basic_expr:
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frontend_verilog_yyerror("Syntax error.");
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frontend_verilog_yyerror("Syntax error.");
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AstNode *bits = new AstNode(AST_IDENTIFIER);
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AstNode *bits = new AstNode(AST_IDENTIFIER);
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bits->str = *$1;
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bits->str = *$1;
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AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
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AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true);
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if (val == NULL)
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if (val == NULL)
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log_error("Value conversion failed: `%s'\n", $2->c_str());
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log_error("Value conversion failed: `%s'\n", $2->c_str());
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$$ = new AstNode(AST_TO_BITS, bits, val);
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$$ = new AstNode(AST_TO_BITS, bits, val);
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@ -1270,14 +1270,14 @@ basic_expr:
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delete $2;
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delete $2;
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} |
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} |
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TOK_CONST TOK_CONST {
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TOK_CONST TOK_CONST {
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$$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
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$$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true);
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if ($$ == NULL || (*$2)[0] != '\'')
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if ($$ == NULL || (*$2)[0] != '\'')
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log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
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log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str());
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delete $1;
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delete $1;
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delete $2;
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delete $2;
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} |
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} |
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TOK_CONST {
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TOK_CONST {
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$$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
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$$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), true);
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if ($$ == NULL)
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if ($$ == NULL)
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log_error("Value conversion failed: `%s'\n", $1->c_str());
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log_error("Value conversion failed: `%s'\n", $1->c_str());
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delete $1;
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delete $1;
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