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Make return value of $clog2 signed 

As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2018-11-24 18:49:23 +01:00
parent ab97eddee9
commit 86ce43999e
1 changed files with 1 additions and 1 deletions
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frontends/ast/simplify.cc
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@ -1913,7 +1913,7 @@ skip_dynamic_range_lvalue_expansion:;
if (arg_value.bits.at(i) == RTLIL::State::S1) if (arg_value.bits.at(i) == RTLIL::State::S1)
result = i + 1; result = i + 1;
newNode = mkconst_int(result, false); newNode = mkconst_int(result, true);
goto apply_newNode; goto apply_newNode;
} }