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Bugfix in Xilinx LUT mapping

This commit is contained in:
Clifford Wolf 2015-10-30 13:58:03 +01:00
parent 1e32e4bdae
commit 864808992b
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/synth_xilinx.cc
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@ -204,7 +204,7 @@ struct SynthXilinxPass : public Pass {
if (check_label(active, run_from, run_to, "map_luts")) if (check_label(active, run_from, run_to, "map_luts"))
{ {
Pass::call(design, "abc -lut 5:8" + string(retime ? " -dff" : "")); Pass::call(design, "abc -lut 6:8" + string(retime ? " -dff" : ""));
Pass::call(design, "clean"); Pass::call(design, "clean");
} }