From 1f801993e3de7face79882cb10e7a4cb5ccaf985 Mon Sep 17 00:00:00 2001 From: 1138-4EB <1138-4EB@users.noreply.github.com> Date: Mon, 1 Jul 2019 13:21:16 +0200 Subject: [PATCH 01/23] dockerfile: DEBIAN_FRONTEND should not be permanent --- Dockerfile | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/Dockerfile b/Dockerfile index 3c7188d82..65f7d9dbc 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,25 +1,32 @@ FROM ubuntu:18.04 as builder LABEL author="Abdelrahman Hosny " -ENV DEBIAN_FRONTEND=noninteractive -RUN apt-get update && apt-get install -y build-essential \ +RUN apt-get update -qq \ + && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ + ca-certificates \ clang \ bison \ + build-essential \ flex \ - libreadline-dev \ gawk \ - tcl-dev \ - libffi-dev \ git \ + libffi-dev \ + libreadline-dev \ pkg-config \ - python3 && \ - rm -rf /var/lib/apt/lists + python3 \ + tcl-dev \ + && apt-get autoclean && apt-get clean && apt-get -y autoremove \ + && update-ca-certificates \ + && rm -rf /var/lib/apt/lists + COPY . / RUN make && \ make install FROM ubuntu:18.04 -ENV DEBIAN_FRONTEND=noninteractive -RUN apt-get update && apt-get install -y libreadline-dev tcl-dev +RUN apt-get update -qq \ + && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ + libreadline-dev \ + tcl-dev COPY --from=builder /yosys /build/yosys COPY --from=builder /yosys-abc /build/yosys-abc From 34635116014dc178cc7608bc8e1804b294e1a21f Mon Sep 17 00:00:00 2001 From: 1138-4EB <1138-4EB@users.noreply.github.com> Date: Mon, 1 Jul 2019 13:24:28 +0200 Subject: [PATCH 02/23] dockerfile: reduce number of COPY layers --- Dockerfile | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/Dockerfile b/Dockerfile index 65f7d9dbc..2e0eba98c 100644 --- a/Dockerfile +++ b/Dockerfile @@ -19,8 +19,9 @@ RUN apt-get update -qq \ && rm -rf /var/lib/apt/lists COPY . / -RUN make && \ - make install +RUN make \ + && make install \ + && mkdir dist && cp yosys yosys-abc yosys-config yosys-filterlib yosys-smtbmc dist/ FROM ubuntu:18.04 RUN apt-get update -qq \ @@ -28,11 +29,7 @@ RUN apt-get update -qq \ libreadline-dev \ tcl-dev -COPY --from=builder /yosys /build/yosys -COPY --from=builder /yosys-abc /build/yosys-abc -COPY --from=builder /yosys-config /build/yosys-config -COPY --from=builder /yosys-filterlib /build/yosys-filterlib -COPY --from=builder /yosys-smtbmc /build/yosys-smtbmc +COPY --from=builder /dist /build ENV PATH /build:$PATH RUN useradd -m yosys From 5e2919de026aab163f05e2b9440a3bf3563ac4fc Mon Sep 17 00:00:00 2001 From: 1138-4EB <1138-4EB@users.noreply.github.com> Date: Mon, 1 Jul 2019 14:50:15 +0200 Subject: [PATCH 03/23] dockerfile: add ARG IMAGE, use three stages --- Dockerfile | 40 +++++++++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/Dockerfile b/Dockerfile index 2e0eba98c..d21f6dc5b 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,8 +1,24 @@ -FROM ubuntu:18.04 as builder -LABEL author="Abdelrahman Hosny " +ARG IMAGE="ubuntu:18.04" + +#--- + +FROM $IMAGE AS base + RUN apt-get update -qq \ && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ ca-certificates \ + libreadline-dev \ + tcl-dev \ + && apt-get autoclean && apt-get clean && apt-get -y autoremove \ + && update-ca-certificates \ + && rm -rf /var/lib/apt/lists + +#--- + +FROM base AS build + +RUN apt-get update -qq \ + && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ clang \ bison \ build-essential \ @@ -10,28 +26,26 @@ RUN apt-get update -qq \ gawk \ git \ libffi-dev \ - libreadline-dev \ pkg-config \ python3 \ - tcl-dev \ && apt-get autoclean && apt-get clean && apt-get -y autoremove \ - && update-ca-certificates \ && rm -rf /var/lib/apt/lists COPY . / + RUN make \ && make install \ && mkdir dist && cp yosys yosys-abc yosys-config yosys-filterlib yosys-smtbmc dist/ -FROM ubuntu:18.04 -RUN apt-get update -qq \ - && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - libreadline-dev \ - tcl-dev +#--- -COPY --from=builder /dist /build +FROM base + +COPY --from=build /dist /opt/yosys + +ENV PATH /opt/yosys:$PATH -ENV PATH /build:$PATH RUN useradd -m yosys USER yosys -ENTRYPOINT ["yosys"] + +CMD ["yosys"] From 99de39fc79fa948e1f844faa81206532efabc268 Mon Sep 17 00:00:00 2001 From: 1138-4EB <1138-4EB@users.noreply.github.com> Date: Wed, 7 Aug 2019 05:37:00 +0200 Subject: [PATCH 04/23] dockerfile: use PREFIX instead of cp --- Dockerfile | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Dockerfile b/Dockerfile index d21f6dc5b..027514a3b 100644 --- a/Dockerfile +++ b/Dockerfile @@ -31,19 +31,22 @@ RUN apt-get update -qq \ && apt-get autoclean && apt-get clean && apt-get -y autoremove \ && rm -rf /var/lib/apt/lists -COPY . / +COPY . /yosys -RUN make \ +ENV PREFIX /opt/yosys + +RUN cd /yosys \ + && make \ && make install \ - && mkdir dist && cp yosys yosys-abc yosys-config yosys-filterlib yosys-smtbmc dist/ + && make test #--- FROM base -COPY --from=build /dist /opt/yosys +COPY --from=build /opt/yosys /opt/yosys -ENV PATH /opt/yosys:$PATH +ENV PATH /opt/yosys/bin:$PATH RUN useradd -m yosys USER yosys From 36c80cf4561cac321c0b0931b37ecac9dc42e07a Mon Sep 17 00:00:00 2001 From: 1138-4EB <1138-4EB@users.noreply.github.com> Date: Wed, 7 Aug 2019 14:24:09 +0200 Subject: [PATCH 05/23] dockerfile: use 'python:3-slim-buster' base image --- Dockerfile | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Dockerfile b/Dockerfile index 027514a3b..549c73c97 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,4 @@ -ARG IMAGE="ubuntu:18.04" +ARG IMAGE="python:3-slim-buster" #--- @@ -7,8 +7,13 @@ FROM $IMAGE AS base RUN apt-get update -qq \ && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ ca-certificates \ + clang \ + curl \ + libffi-dev \ libreadline-dev \ tcl-dev \ + graphviz \ + xdot \ && apt-get autoclean && apt-get clean && apt-get -y autoremove \ && update-ca-certificates \ && rm -rf /var/lib/apt/lists @@ -19,15 +24,13 @@ FROM base AS build RUN apt-get update -qq \ && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ - clang \ bison \ - build-essential \ flex \ gawk \ + gcc \ git \ - libffi-dev \ + iverilog \ pkg-config \ - python3 \ && apt-get autoclean && apt-get clean && apt-get -y autoremove \ && rm -rf /var/lib/apt/lists From d9c16644626d49b5bb5eb463f2a113e13ad22d69 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 10:08:17 -0700 Subject: [PATCH 06/23] Simplify opt_expr tests using equiv_opt --- tests/opt/opt_expr.ys | 95 +++++++++++-------------------------------- 1 file changed, 23 insertions(+), 72 deletions(-) diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 0c61ac881..9f3c0a1cd 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -6,24 +6,16 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine +equiv_opt -assert opt_expr -fine +design -load postopt + wreduce - select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - ########## +design -reset read_verilog < Date: Fri, 9 Aug 2019 10:13:49 -0700 Subject: [PATCH 07/23] Cleanup some more --- tests/opt/opt_expr.ys | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 9f3c0a1cd..28d57f530 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -5,8 +5,6 @@ module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -22,8 +20,6 @@ module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, outp endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -39,8 +35,6 @@ module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -56,8 +50,6 @@ module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, out endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -73,8 +65,6 @@ module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -90,8 +80,6 @@ module opt_expr_sub_test4(input [3:0] i, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt From 93001116011d46e50c0a24b0bd21c2f07746dc42 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 10:22:06 -0700 Subject: [PATCH 08/23] Add new $alu test, remove wreduce --- tests/opt/opt_expr.ys | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 28d57f530..96ab2f31a 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -8,8 +8,22 @@ EOT equiv_opt -assert opt_expr -fine design -load postopt -wreduce -select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i +select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i + +########## + +design -reset +read_verilog < Date: Fri, 9 Aug 2019 10:30:53 -0700 Subject: [PATCH 09/23] Add alumacc versions of opt_expr tests --- tests/opt/opt_expr.ys | 84 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 96ab2f31a..9f5e845ca 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -12,6 +12,7 @@ select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i ########## +# alumacc version of above design -reset read_verilog < Date: Fri, 9 Aug 2019 10:32:12 -0700 Subject: [PATCH 10/23] opt_expr -fine to trim LSBs of $alu too --- passes/opt/opt_expr.cc | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index acdc39937..5a82b7066 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -642,26 +642,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type.in("$add", "$sub")) { + if (cell->type.in("$add", "$sub", "$alu")) + { RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); - bool sub = cell->type == "$sub"; + bool ignore_a = cell->type == "$sub" || (cell->type == "$alu" && !cell->getPort("\\BI").is_fully_zero()); int i; for (i = 0; i < GetSize(sig_y); i++) { if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) module->connect(sig_y[i], sig_a[i]); - else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) + else if (!ignore_a && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) module->connect(sig_y[i], sig_b[i]); else break; } if (i > 0) { - cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); + cover_list("opt.opt_expr.fine", "$add", "$sub", "$alu", cell->type.str()); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\Y", sig_y.extract_end(i)); + if (cell->type == "$alu") { + cell->setPort("\\X", cell->getPort("\\X").extract_end(i)); + cell->setPort("\\CO", cell->getPort("\\CO").extract_end(i)); + } cell->fixup_parameters(); did_something = true; } From 0adf81cb91cc4068cff342bf880ba68b17d183c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 12:13:17 -0700 Subject: [PATCH 11/23] Add $alu tests --- tests/opt/opt_expr.ys | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 9f5e845ca..f0306efa1 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -179,3 +179,45 @@ equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i + +########### + +design -reset +read_verilog -icells < Date: Fri, 9 Aug 2019 12:13:32 -0700 Subject: [PATCH 12/23] Separate $alu handling --- passes/opt/opt_expr.cc | 57 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 7 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 5a82b7066..0ddfa5e4c 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -642,31 +642,74 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } - if (cell->type.in("$add", "$sub", "$alu")) + if (cell->type.in("$add", "$sub")) { RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); - bool ignore_a = cell->type == "$sub" || (cell->type == "$alu" && !cell->getPort("\\BI").is_fully_zero()); + bool sub = cell->type == "$sub"; int i; for (i = 0; i < GetSize(sig_y); i++) { if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) module->connect(sig_y[i], sig_a[i]); - else if (!ignore_a && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) + else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) module->connect(sig_y[i], sig_b[i]); else break; } if (i > 0) { - cover_list("opt.opt_expr.fine", "$add", "$sub", "$alu", cell->type.str()); + cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\Y", sig_y.extract_end(i)); - if (cell->type == "$alu") { - cell->setPort("\\X", cell->getPort("\\X").extract_end(i)); - cell->setPort("\\CO", cell->getPort("\\CO").extract_end(i)); + cell->fixup_parameters(); + did_something = true; + } + } + + if (cell->type == "$alu") + { + RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); + RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigBit sig_ci = assign_map(cell->getPort("\\CI")); + RTLIL::SigBit sig_bi = assign_map(cell->getPort("\\BI")); + RTLIL::SigSpec sig_x = cell->getPort("\\X"); + RTLIL::SigSpec sig_y = cell->getPort("\\Y"); + RTLIL::SigSpec sig_co = cell->getPort("\\CO"); + + if (sig_ci.wire || sig_bi.wire) + goto next_cell; + + bool sub = (sig_ci == State::S1 && sig_bi == State::S1); + + // If not a subtraction, yet there is a carry or B is inverted + // then no optimisation is possible as carry is not constant + if (!sub && (sig_ci != State::S0 || sig_bi != State::S0)) + goto next_cell; + + int i; + for (i = 0; i < GetSize(sig_y); i++) { + if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) { + module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]); + module->connect(sig_y[i], sig_a[i]); + module->connect(sig_co[i], sub ? State::S1 : State::S0); } + else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) { + module->connect(sig_x[i], sig_b[i]); + module->connect(sig_y[i], sig_b[i]); + module->connect(sig_co[i], State::S0); + } + else + break; + } + if (i > 0) { + cover_list("opt.opt_expr.fine", "$alu", cell->type.str()); + cell->setPort("\\A", sig_a.extract_end(i)); + cell->setPort("\\B", sig_b.extract_end(i)); + cell->setPort("\\X", sig_x.extract_end(i)); + cell->setPort("\\Y", sig_y.extract_end(i)); + cell->setPort("\\CO", sig_co.extract_end(i)); cell->fixup_parameters(); did_something = true; } From 849e0eeab4408ed23d16abbf9d98a3603b770514 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 12:43:21 -0700 Subject: [PATCH 13/23] Grammar --- passes/opt/opt_expr.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 0ddfa5e4c..66f360f6e 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -684,7 +684,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons bool sub = (sig_ci == State::S1 && sig_bi == State::S1); // If not a subtraction, yet there is a carry or B is inverted - // then no optimisation is possible as carry is not constant + // then no optimisation is possible as carry will not be constant if (!sub && (sig_ci != State::S0 || sig_bi != State::S0)) goto next_cell; From 02b0d328ad4eadd2011344ef30e718262932cff8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 10 Aug 2019 08:26:41 -0700 Subject: [PATCH 14/23] cover_list -> cover as per @cliffordwolf --- passes/opt/opt_expr.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 66f360f6e..c803b5d3d 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -659,7 +659,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); + cover("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\Y", sig_y.extract_end(i)); @@ -704,7 +704,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover_list("opt.opt_expr.fine", "$alu", cell->type.str()); + cover_list("opt.opt_expr.fine.$alu"); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\X", sig_x.extract_end(i)); From 282cc77604a9a855c303869321d4179790b0b64b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 10 Aug 2019 11:55:00 -0700 Subject: [PATCH 15/23] Wrong way around --- passes/opt/opt_expr.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index c803b5d3d..29510fe81 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -659,7 +659,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); + cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str()); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\Y", sig_y.extract_end(i)); @@ -704,7 +704,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons break; } if (i > 0) { - cover_list("opt.opt_expr.fine.$alu"); + cover("opt.opt_expr.fine.$alu"); cell->setPort("\\A", sig_a.extract_end(i)); cell->setPort("\\B", sig_b.extract_end(i)); cell->setPort("\\X", sig_x.extract_end(i)); From e4a09715814d4fa9019c69d2305973030755c379 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 12 Aug 2019 11:17:15 -0700 Subject: [PATCH 16/23] Since $_ANDNOT_ is not symmetric, do not sort leaves --- passes/techmap/extract_fa.cc | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index b541ceb6b..befaf68a4 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -153,12 +153,10 @@ struct ExtractFaWorker } } - void check_partition(SigBit root, pool &leaves) + void check_partition(SigBit root, const pool &leaves) { if (config.enable_ha && GetSize(leaves) == 2) { - leaves.sort(); - SigBit A = SigSpec(leaves)[0]; SigBit B = SigSpec(leaves)[1]; @@ -196,8 +194,6 @@ struct ExtractFaWorker if (config.enable_fa && GetSize(leaves) == 3) { - leaves.sort(); - SigBit A = SigSpec(leaves)[0]; SigBit B = SigSpec(leaves)[1]; SigBit C = SigSpec(leaves)[2]; @@ -237,7 +233,7 @@ struct ExtractFaWorker } } - void find_partitions(SigBit root, pool &leaves, pool> &cache, int maxdepth, int maxbreadth) + void find_partitions(SigBit root, const pool &leaves, pool> &cache, int maxdepth, int maxbreadth) { if (cache.count(leaves)) return; @@ -293,8 +289,8 @@ struct ExtractFaWorker continue; SigBit root = it.first; - pool leaves = { root }; - pool> cache; + const pool leaves = { root }; + pool> cache; if (config.verbose) log(" checking %s\n", log_signal(it.first)); From 0e128510c0f4441014dd8e07fe820efe0304f28a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 14 Aug 2019 10:40:53 -0700 Subject: [PATCH 17/23] Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves" --- passes/techmap/extract_fa.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index befaf68a4..b541ceb6b 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -153,10 +153,12 @@ struct ExtractFaWorker } } - void check_partition(SigBit root, const pool &leaves) + void check_partition(SigBit root, pool &leaves) { if (config.enable_ha && GetSize(leaves) == 2) { + leaves.sort(); + SigBit A = SigSpec(leaves)[0]; SigBit B = SigSpec(leaves)[1]; @@ -194,6 +196,8 @@ struct ExtractFaWorker if (config.enable_fa && GetSize(leaves) == 3) { + leaves.sort(); + SigBit A = SigSpec(leaves)[0]; SigBit B = SigSpec(leaves)[1]; SigBit C = SigSpec(leaves)[2]; @@ -233,7 +237,7 @@ struct ExtractFaWorker } } - void find_partitions(SigBit root, const pool &leaves, pool> &cache, int maxdepth, int maxbreadth) + void find_partitions(SigBit root, pool &leaves, pool> &cache, int maxdepth, int maxbreadth) { if (cache.count(leaves)) return; @@ -289,8 +293,8 @@ struct ExtractFaWorker continue; SigBit root = it.first; - const pool leaves = { root }; - pool> cache; + pool leaves = { root }; + pool> cache; if (config.verbose) log(" checking %s\n", log_signal(it.first)); From 0c003a3d0d3e2e2b21ac03404f245a5ab1189bc7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 14 Aug 2019 11:26:32 -0700 Subject: [PATCH 18/23] Bump gcc from 4.8 to 4.9 as undefined reference ... to `__warn_memset_zero_len'. Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0 --- .travis.yml | 43 +++++++------------------------------------ 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/.travis.yml b/.travis.yml index 4102f05fe..516df54d8 100644 --- a/.travis.yml +++ b/.travis.yml @@ -18,7 +18,7 @@ matrix: addons: apt: packages: - - g++-4.8 + - g++-4.9 - gperf - build-essential - bison @@ -38,36 +38,7 @@ matrix: - libboost-filesystem-dev - zlib1g-dev env: - - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8" - - # Latest gcc-6 on Travis Linux - - os: linux - addons: - apt: - sources: - - ubuntu-toolchain-r-test - packages: - - g++-6 - - gperf - - build-essential - - bison - - flex - - libreadline-dev - - gawk - - tcl-dev - - libffi-dev - - git - - graphviz - - xdot - - pkg-config - - python - - python3 - - libboost-system-dev - - libboost-python-dev - - libboost-filesystem-dev - - zlib1g-dev - env: - - MATRIX_EVAL="CONFIG=gcc && CC=gcc-6 && CXX=g++-6" + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9" # Latest gcc supported on Travis Linux - os: linux @@ -76,7 +47,7 @@ matrix: sources: - ubuntu-toolchain-r-test packages: - - g++-7 + - g++-9 - gperf - build-essential - bison @@ -96,7 +67,7 @@ matrix: - libboost-filesystem-dev - zlib1g-dev env: - - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7" + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-9 && CXX=g++-9" # Clang which ships on Trusty Linux - os: linux @@ -133,9 +104,9 @@ matrix: addons: apt: sources: - - llvm-toolchain-trusty-5.0 + - llvm-toolchain-bionic-8.0 packages: - - clang-5.0 + - clang-8.0 - gperf - build-essential - bison @@ -155,7 +126,7 @@ matrix: - libboost-filesystem-dev - zlib1g-dev env: - - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0" + - MATRIX_EVAL="CONFIG=clang && CC=clang-8.0 && CXX=clang++-8.0" # # Latest clang on Mac OS X # - os: osx From 2df432af03eba4604543aa04ba99e35c952253e1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 14 Aug 2019 11:52:08 -0700 Subject: [PATCH 19/23] bionic -> xenial as its on whitelist --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 516df54d8..8d1ad3006 100644 --- a/.travis.yml +++ b/.travis.yml @@ -104,7 +104,7 @@ matrix: addons: apt: sources: - - llvm-toolchain-bionic-8.0 + - llvm-toolchain-xenial-8 packages: - clang-8.0 - gperf From c82b2fa31f8965be2680c87af6cd9ac5d26ead4d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 14 Aug 2019 12:16:02 -0700 Subject: [PATCH 20/23] Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! --- .travis.yml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index 8d1ad3006..bf6657b1e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -13,12 +13,14 @@ env: matrix: include: - # Latest gcc-4.8, earliest version supported by Travis + # Earliest gcc version that works + # 4.8 and 4.9 fails to compile iverilog giving: + # "undefined reference to `__warn_memset_zero_len'" - os: linux addons: apt: packages: - - g++-4.9 + - g++-5 - gperf - build-essential - bison @@ -38,7 +40,7 @@ matrix: - libboost-filesystem-dev - zlib1g-dev env: - - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9" + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-5 && CXX=g++-5" # Latest gcc supported on Travis Linux - os: linux From e517c1c91377190418fed06f09c13cdc716b2fb7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 14 Aug 2019 12:23:15 -0700 Subject: [PATCH 21/23] Remove .0 from clang-8.0 --- .travis.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.yml index bf6657b1e..46bbcf9c3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -108,7 +108,7 @@ matrix: sources: - llvm-toolchain-xenial-8 packages: - - clang-8.0 + - clang-8 - gperf - build-essential - bison @@ -128,7 +128,7 @@ matrix: - libboost-filesystem-dev - zlib1g-dev env: - - MATRIX_EVAL="CONFIG=clang && CC=clang-8.0 && CXX=clang++-8.0" + - MATRIX_EVAL="CONFIG=clang && CC=clang-8 && CXX=clang++-8" # # Latest clang on Mac OS X # - os: osx From 182659f1141752a8b35fe6816fdbc7aef113ff77 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 14 Aug 2019 12:26:45 -0700 Subject: [PATCH 22/23] Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" This reverts commit c82b2fa31f8965be2680c87af6cd9ac5d26ead4d. --- .travis.yml | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/.travis.yml b/.travis.yml index 46bbcf9c3..f5cac3eb2 100644 --- a/.travis.yml +++ b/.travis.yml @@ -13,14 +13,12 @@ env: matrix: include: - # Earliest gcc version that works - # 4.8 and 4.9 fails to compile iverilog giving: - # "undefined reference to `__warn_memset_zero_len'" + # Latest gcc-4.8, earliest version supported by Travis - os: linux addons: apt: packages: - - g++-5 + - g++-4.9 - gperf - build-essential - bison @@ -40,7 +38,7 @@ matrix: - libboost-filesystem-dev - zlib1g-dev env: - - MATRIX_EVAL="CONFIG=gcc && CC=gcc-5 && CXX=g++-5" + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9" # Latest gcc supported on Travis Linux - os: linux From 4c2a2e275f67778bcfb40a983d9ba868cbe04ebc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 14 Aug 2019 12:28:17 -0700 Subject: [PATCH 23/23] Revert earliest to gcc-4.8, compile iverilog with default compiler --- .travis.yml | 4 ++-- .travis/setup.sh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.travis.yml b/.travis.yml index f5cac3eb2..09f380831 100644 --- a/.travis.yml +++ b/.travis.yml @@ -18,7 +18,7 @@ matrix: addons: apt: packages: - - g++-4.9 + - g++-4.8 - gperf - build-essential - bison @@ -38,7 +38,7 @@ matrix: - libboost-filesystem-dev - zlib1g-dev env: - - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.9 && CXX=g++-4.9" + - MATRIX_EVAL="CONFIG=gcc && CC=gcc-4.8 && CXX=g++-4.8" # Latest gcc supported on Travis Linux - os: linux diff --git a/.travis/setup.sh b/.travis/setup.sh index 4af0b8ee9..02879b974 100755 --- a/.travis/setup.sh +++ b/.travis/setup.sh @@ -51,7 +51,7 @@ fi git clone git://github.com/steveicarus/iverilog.git cd iverilog autoconf - ./configure --prefix=$HOME/.local-bin + CC=gcc CXX=g++ ./configure --prefix=$HOME/.local-bin make make install echo