mirror of https://github.com/YosysHQ/yosys.git
Optimize compares to powers of 2
Remove opt_compare and put comparison pass in opt_expr
assuming a [7:0] is unsigned
a >= (1<<x) becomes |a[7:x]
a < (1<<x) becomes !a[7:x]
Additionally:
a >= 0 becomes constant true,
a < 0 becomes constant false
delete opt_compare.cc
revert opt.cc to commit b7cfb7dbd
(remove opt_compare step)
This commit is contained in:
parent
943389cdd5
commit
84f9cd0025
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@ -6,7 +6,6 @@ OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_rmdff.o
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OBJS += passes/opt/opt_rmdff.o
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OBJS += passes/opt/opt_clean.o
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OBJS += passes/opt/opt_clean.o
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OBJS += passes/opt/opt_expr.o
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OBJS += passes/opt/opt_expr.o
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OBJS += passes/opt/opt_compare.o
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ifneq ($(SMALL),1)
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ifneq ($(SMALL),1)
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OBJS += passes/opt/share.o
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OBJS += passes/opt/share.o
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@ -128,7 +128,6 @@ struct OptPass : public Pass {
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{
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{
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while (1) {
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while (1) {
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Pass::call(design, "opt_expr" + opt_expr_args);
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Pass::call(design, "opt_expr" + opt_expr_args);
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Pass::call(design, "opt_compare");
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Pass::call(design, "opt_merge" + opt_merge_args);
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Pass::call(design, "opt_merge" + opt_merge_args);
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design->scratchpad_unset("opt.did_something");
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design->scratchpad_unset("opt.did_something");
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Pass::call(design, "opt_rmdff" + opt_rmdff_args);
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Pass::call(design, "opt_rmdff" + opt_rmdff_args);
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@ -142,7 +141,6 @@ struct OptPass : public Pass {
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else
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else
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{
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{
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Pass::call(design, "opt_expr" + opt_expr_args);
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Pass::call(design, "opt_expr" + opt_expr_args);
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Pass::call(design, "opt_compare");
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Pass::call(design, "opt_merge -nomux" + opt_merge_args);
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Pass::call(design, "opt_merge -nomux" + opt_merge_args);
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while (1) {
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while (1) {
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design->scratchpad_unset("opt.did_something");
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design->scratchpad_unset("opt.did_something");
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@ -1,78 +0,0 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void replace_le_cell(Cell* cell, Module* module){
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RTLIL::SigSpec a = cell->getPort("\\A");
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RTLIL::SigSpec b = cell->getPort("\\B");
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RTLIL::SigSpec y(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
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if(b.is_fully_const() && b.is_fully_zero() ){
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if(cell->parameters["\\A_SIGNED"].as_bool()){
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// a < 0, can be replaced with a[MAX_BIT]
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log("Found x < 0 (signed), replacing with the last bit\n");
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int a_width = cell->parameters["\\A_WIDTH"].as_int();
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if(a_width > 0){
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y[0] = a[a_width-1];
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module->connect(cell->getPort("\\Y"), y);
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module->remove(cell);
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}
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}
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}
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}
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void replace_ge_cell(Cell* cell, Module* module){
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RTLIL::SigSpec a = cell->getPort("\\A");
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RTLIL::SigSpec b = cell->getPort("\\B");
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RTLIL::SigSpec y = cell->getPort("\\Y");
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if(b.is_fully_const() && b.is_fully_zero()){
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if(cell->parameters["\\A_SIGNED"].as_bool()){
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log("Found x >= 0 (signed), optimizing\n");
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RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
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int a_width = cell->parameters["\\A_WIDTH"].as_int();
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if(a_width > 0){
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a_prime[0] = a[a_width-1];
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module->remove(cell);
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module->addNot("$not", a_prime, y,false);
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}
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}
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}
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}
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void optimize_compares(Design* design, Module* module){
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log_header(design, "Executing OPT_COMPARE pass.\n");
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log_push();
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TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
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for(auto cell: module->cells())
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if(design->selected(module,cell) && cell->type[0] == '$'){
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cells.node(cell);
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}
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cells.sort();
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for (auto cell: cells.sorted){
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if (cell->type == "$lt"){
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replace_le_cell(cell,module);
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}
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else if(cell->type == "$ge"){
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replace_ge_cell(cell,module);
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}
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}
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}
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struct OptCompare : public Pass {
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OptCompare() : Pass("opt_compare") {}
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virtual void execute(vector<string>, Design* design){
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for(auto module: design->selected_modules())
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optimize_compares(design,module);
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}
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virtual void help() {
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log("\n");
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log("opt_compare\n");
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log("\n");
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log("This pass optimizes some signed compares with 0.\n");
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log("In particular, it replaces a < 0 with the msb of a,\n");
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log("and a >= 0 with the inverted msb of a.\n");
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log("\n");
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}
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} OptCompare;
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PRIVATE_NAMESPACE_END
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@ -1166,6 +1166,67 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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}
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}
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}
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}
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//replace a <0 or a >=0 with the top bit of a
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if(do_fine && (cell->type == "$lt" || cell->type == "$ge"))
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{
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bool is_lt = cell->type == "$lt" ? 1 : 0;
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RTLIL::SigSpec a = cell->getPort("\\A");
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RTLIL::SigSpec b = cell->getPort("\\B");
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int a_width = cell->parameters["\\A_WIDTH"].as_int();
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//replace a(signed) < 0 with the high bit of a
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if(b.is_fully_const() && b.is_fully_zero() && cell->parameters["\\A_SIGNED"].as_bool() == true){
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RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
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a_prime[0] = a[a_width-1];
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if(is_lt){
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log("Optimizing a < 0 with a[%d]\n",a_width - 1);
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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}
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else{
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log("Optimizing a >= 0 with ~a[%d]\n",a_width - 1);
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module->addNot("$not", a_prime, cell->getPort("\\Y"));
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module->remove(cell);
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}
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did_something = true;
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goto next_cell;
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}
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else if(b.is_fully_const() && b.is_fully_def() && cell->parameters["\\A_SIGNED"].as_bool() == false){
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int b_value = b.as_int(false);
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if(b_value == 0){
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RTLIL::SigSpec a_prime(RTLIL::State::S0,1);
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if(is_lt){
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log("replacing a(unsigned) < 0 with constant false\n");
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a_prime[0] = RTLIL::State::S0;
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}
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else{
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log("replacing a(unsigned) >= 0 with constant true\n");
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a_prime[0] = RTLIL::State::S1;
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}
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module->connect(cell->getPort("\\Y"), a_prime);
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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else if((b_value & -b_value) == b_value){ //if b has only 1 bit set
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int bit_set = ceil_log2(b_value);
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RTLIL::SigSpec a_prime(RTLIL::State::S0,a_width-bit_set);
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for(int i = bit_set; i < a_width; i++){
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a_prime[i-bit_set] = a[i];
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}
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if(is_lt){
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log("replacing a < %d with !a[%d:%d]\n",b_value,a_width-1,bit_set);
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module->addLogicNot("$logic_not", a_prime,cell->getPort("\\Y"));
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}
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else{
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log("replacing a >= %d with |a[%d:%d]\n",b_value,a_width-1,bit_set);
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module->addReduceOr("$reduce_or", a_prime,cell->getPort("\\Y"));
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}
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module->remove(cell);
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did_something = true;
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goto next_cell;
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}
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}
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}
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next_cell:;
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next_cell:;
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#undef ACTION_DO
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#undef ACTION_DO
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