mirror of https://github.com/YosysHQ/yosys.git
Fix begin/end in generate
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@ -21,9 +21,6 @@ module top;
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end
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end
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generate
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begin : unconditional_block
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initial `CONSTANT_CHECK
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end
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if (WIDTH == 32) begin : conditional_block
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initial `CONSTANT_CHECK
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end
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@ -167,7 +167,7 @@ module gen_test7;
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reg [2:0] out2;
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wire [2:0] out3;
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generate
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begin : cond
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if (1) begin : cond
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reg [2:0] sub_out1;
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reg [2:0] sub_out2;
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wire [2:0] sub_out3;
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@ -215,9 +215,9 @@ module gen_test8;
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wire [1:0] x = 2'b11;
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generate
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begin : A
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if (1) begin : A
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wire [1:0] x;
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begin : B
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if (1) begin : B
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wire [1:0] x = 2'b00;
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`ASSERT(x == 0)
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`ASSERT(A.x == 2)
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@ -228,7 +228,7 @@ module gen_test8;
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`ASSERT(gen_test8.A.C.x == 1)
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`ASSERT(gen_test8.A.B.x == 0)
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end
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begin : C
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if (1) begin : C
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wire [1:0] x = 2'b01;
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`ASSERT(x == 1)
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`ASSERT(A.x == 2)
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