riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

extract_fa: Simplify xor2/xnor2 negation

This commit is contained in:
Øystein Hovind 2024-10-30 17:31:00 +01:00
parent 64d298e2e9
commit 84d0c8fbfc
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
passes/techmap/extract_fa.cc
View File

@ -517,14 +517,15 @@ struct ExtractFaWorker
cell->setPort(ID::Y, Y); cell->setPort(ID::Y, Y);
} }
auto invert_y = f2i.inv_a ^ f2i.inv_b;
if (func2.at(key).count(xor2_func)) { if (func2.at(key).count(xor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y; SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
for (auto bit : func2.at(key).at(xor2_func)) for (auto bit : func2.at(key).at(xor2_func))
assign_new_driver(bit, YY); assign_new_driver(bit, YY);
} }
if (func2.at(key).count(xnor2_func)) { if (func2.at(key).count(xnor2_func)) {
SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y); SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
for (auto bit : func2.at(key).at(xnor2_func)) for (auto bit : func2.at(key).at(xnor2_func))
assign_new_driver(bit, YY); assign_new_driver(bit, YY);
} }