mirror of https://github.com/YosysHQ/yosys.git
Fixed a bug in "add -global_input"
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parent
64a5f8f75e
commit
84ced2bb8e
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@ -23,12 +23,11 @@
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static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
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static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
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{
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{
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RTLIL::Wire *wire = NULL;
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name = RTLIL::escape_id(name);
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name = RTLIL::escape_id(name);
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if (module->count_id(name) != 0)
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if (module->count_id(name) != 0)
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{
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{
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RTLIL::Wire *wire = NULL;
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if (module->wires.count(name) > 0)
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if (module->wires.count(name) > 0)
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wire = module->wires.at(name);
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wire = module->wires.at(name);
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@ -43,24 +42,26 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
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if (wire == NULL)
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if (wire == NULL)
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log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
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log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str());
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log("Skipping module %s as it already has such an object.\n", module->name.c_str());
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return;
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log("Module %s already has such an object.\n", module->name.c_str());
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}
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}
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else
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{
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wire = new RTLIL::Wire;
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wire->name = name;
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wire->width = width;
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wire->port_input = flag_input;
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wire->port_output = flag_output;
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module->add(wire);
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RTLIL::Wire *wire = new RTLIL::Wire;
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if (flag_input || flag_output) {
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wire->name = name;
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wire->port_id = module->wires.size();
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wire->width = width;
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module->fixup_ports();
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wire->port_input = flag_input;
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}
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wire->port_output = flag_output;
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module->add(wire);
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if (flag_input || flag_output) {
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log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
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wire->port_id = module->wires.size();
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module->fixup_ports();
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}
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}
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log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
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if (!flag_global)
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if (!flag_global)
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return;
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return;
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