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This commit is contained in:
Eddie Hung 2019-08-09 12:43:21 -07:00
parent 31f6d74552
commit 849e0eeab4
1 changed files with 1 additions and 1 deletions
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2
passes/opt/opt_expr.cc
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@ -684,7 +684,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
bool sub = (sig_ci == State::S1 && sig_bi == State::S1); bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
// If not a subtraction, yet there is a carry or B is inverted // If not a subtraction, yet there is a carry or B is inverted
// then no optimisation is possible as carry is not constant // then no optimisation is possible as carry will not be constant
if (!sub && (sig_ci != State::S0 || sig_bi != State::S0)) if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
goto next_cell; goto next_cell;