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Improve naming scheme for (VHDL) modules imported from Verific 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-10-24 12:13:37 +02:00
parent 34dadd9ab2
commit 84982b3083
1 changed files with 26 additions and 3 deletions
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29
frontends/verific/verific.cc
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@ -787,7 +787,18 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo) void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo)
{ {
std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name(); std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name();
std::string module_name = nl->IsOperator() ? "$verific$" + netlist_name : RTLIL::escape_id(netlist_name); std::string module_name = netlist_name;
if (nl->IsOperator()) {
module_name = "$verific$" + module_name;
} else {
if (*nl->Name()) {
module_name += "(";
module_name += nl->Name();
module_name += ")";
}
module_name = "\\" + module_name;
}
netlist = nl; netlist = nl;
@ -1396,8 +1407,20 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
import_verific_cells: import_verific_cells:
nl_todo.insert(inst->View()); nl_todo.insert(inst->View());
RTLIL::Cell *cell = module->addCell(inst_name, inst->IsOperator() ? std::string inst_type = inst->View()->Owner()->Name();
std::string("$verific$") + inst->View()->Owner()->Name() : RTLIL::escape_id(inst->View()->Owner()->Name()));
if (inst->View()->IsOperator()) {
inst_type = "$verific$" + inst_type;
} else {
if (*inst->View()->Name()) {
inst_type += "(";
inst_type += inst->View()->Name();
inst_type += ")";
}
inst_type = "\\" + inst_type;
}
RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
if (inst->IsPrimitive() && mode_keep) if (inst->IsPrimitive() && mode_keep)
cell->attributes["\\keep"] = 1; cell->attributes["\\keep"] = 1;