mirror of https://github.com/YosysHQ/yosys.git
Workaround issues exposed by gcc-4.8
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@ -114,13 +114,20 @@ struct ConstEvalAig
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RTLIL::Cell *cell = sig2driver.at(output);
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RTLIL::Cell *cell = sig2driver.at(output);
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RTLIL::SigBit sig_a = cell->getPort("\\A");
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RTLIL::SigBit sig_a = cell->getPort("\\A");
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sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
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sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
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if (!inputs.count(sig_a))
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if (!inputs.count(sig_a))
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compute_deps(sig_a, inputs);
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compute_deps(sig_a, inputs);
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if (cell->type == "$_AND_") {
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if (cell->type == "$_AND_") {
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
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// that may occur does so here, and
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// not mid insertion (below)
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sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
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sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
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if (!inputs.count(sig_b))
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if (!inputs.count(sig_b))
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compute_deps(sig_b, inputs);
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compute_deps(sig_b, inputs);
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}
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}
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