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Re-enabled mux->and/or transform (and fixed lm32 in yosys-bigsim)

This commit is contained in:
Clifford Wolf 2015-01-13 13:20:09 +01:00
parent dfa42e272c
commit 8426884b40
1 changed files with 0 additions and 5 deletions
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5
passes/opt/opt_const.cc
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@ -681,10 +681,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
goto next_cell;
}
#if 0
// disabled because replacing muxes with and/or gates sometimes causes probems with
// simulating undefs (e.g. lm32 from yosys-bigsim vs. icarus verilog init problems)
if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type.str());
log("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
@ -724,7 +720,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
did_something = true;
goto next_cell;
}
#endif
if (mux_undef && (cell->type == "$mux" || cell->type == "$pmux")) {
RTLIL::SigSpec new_a, new_b, new_s;