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Use built-in async2sync call as per #1417
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@ -4,11 +4,7 @@ design -save read
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proc
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proc
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async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
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async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
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flatten
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flatten
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synth_xilinx
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -load read
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synth_xilinx
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synth_xilinx
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flatten
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flatten
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