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Update xilinx for ABC9

This commit is contained in:
Eddie Hung 2020-02-13 09:56:30 -08:00
parent ac24a23e31
commit 8408c13405
3 changed files with 16 additions and 20 deletions
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11
techlibs/xilinx/abc9_model.v
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@ -38,17 +38,6 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
endspecify
endmodule
module \$__ABC9_FF_ (input D, output Q);
endmodule
(* abc9_box *)
module \$__ABC9_DELAY (input I, output O);
parameter DELAY = 0;
specify
(I => O) = DELAY;
endspecify
endmodule
// Box to emulate async behaviour of FDC*
(* abc9_box, lib_whitebox *)
module \$__ABC9_ASYNC0 (input A, S, output Y);

23
techlibs/xilinx/cells_sim.v
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@ -227,6 +227,9 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
endspecify
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=5 *)
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
@ -262,20 +265,24 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
assign O5 = I0 ? s5_1[1] : s5_1[0];
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=10 *)
module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
specify
// https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
(I0 => O) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(I1 => O) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(I2 => O) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(I3 => O) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(I4 => O) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(I5 => O) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(I6 => O) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
(I0 => O) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I1 => O) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I2 => O) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I3 => O) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I4 => O) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I5 => O) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I6 => O) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
endspecify
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=20 *)
module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
specify
@ -489,7 +496,7 @@ module FDRE (
//$setup(D , negedge C &&& CE &&& IS_C_INVERTED , -46); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge C &&& !IS_C_INVERTED, 109);
$setup(CE, negedge C &&& IS_C_INVERTED , 109);
$setup(CE, negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(R , posedge C &&& !IS_C_INVERTED, 404);
$setup(R , negedge C &&& IS_C_INVERTED, 404);

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -619,7 +619,7 @@ struct SynthXilinxPass : public ScriptPass
if (dff_mode)
techmap_args += " -D DFF_MODE";
run("techmap " + techmap_args);
run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
std::string abc9_opts;
auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
if (active_design->scratchpad.count(k))