mirror of https://github.com/YosysHQ/yosys.git
Added constant-clock case to opt_rmdff
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@ -92,6 +92,14 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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}
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}
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}
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}
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if (sig_c.is_fully_const()) {
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if (val_rv.bits.size() == 0)
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val_rv = RTLIL::Const(RTLIL::State::Sx, sig_q.width);
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connections.push_back(conn);
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goto delete_dff;
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}
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if (sig_d.is_fully_undef() && sig_d.width == int(val_rv.bits.size())) {
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if (sig_d.is_fully_undef() && sig_d.width == int(val_rv.bits.size())) {
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RTLIL::SigSig conn(sig_q, val_rv);
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connections.push_back(conn);
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mod->connections.push_back(conn);
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